| Selective fault tolerance for register files of graphics processing units M Goncalves, F Fernandes, I Lamb, P Rech, JR Azambuja IEEE Transactions on Nuclear Science 66 (7), 1449-1456, 2019 | 11 | 2019 |
| Improving selective fault tolerance in GPU register files by relaxing application accuracy MM Goncalves, IP Lamb, P Rech, RM Brum, JR Azambuja IEEE Transactions on Nuclear Science 67 (7), 1573-1580, 2020 | 8 | 2020 |
| Protecting virtual programmable switches from cross-app poisoning (cap) attacks IP Lamb, M Saquetti, GB de Oliveira, JR Azambuja, W Cordeiro NOMS 2022-2022 IEEE/IFIP Network Operations and Management Symposium, 1-9, 2022 | 2 | 2022 |
| Managing virtual programmable switches: Principles, requirements, and design directions G Bueno, M Saquetti, P Rodrigues, I Lamb, L Gaspary, MC Luizelli, ... IEEE Communications Magazine 60 (2), 53-59, 2022 | 2 | 2022 |
| Evaluating the Impact of Accuracy Relaxation in the Reliability of GPU Register Files M Goncalves, I Lamb, RM Brum, JR Azambuja 2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019 | 1 | 2019 |
| Control Plane Abstraction for Programable Virtual Switches IP Lamb | | 2020 |
