| Vertical tunnel FET: Design optimization with triple metal-gate layers E Ko, H Lee, JD Park, C Shin IEEE Transactions on Electron Devices 63 (12), 5030-5035, 2016 | 102 | 2016 |
| Sub-60-mV/decade negative capacitance FinFET with sub-10-nm hafnium-based ferroelectric capacitor E Ko, H Lee, Y Goh, S Jeon, C Shin IEEE Journal of the Electron Devices Society 5 (5), 306-309, 2017 | 73 | 2017 |
| Study of random variation in germanium-source vertical tunnel FET H Lee, JD Park, C Shin IEEE Transactions on Electron Devices 63 (5), 1827-1834, 2016 | 48 | 2016 |
| Current-voltage model for negative capacitance field-effect transistors H Lee, Y Yoon, C Shin IEEE Electron Device Letters 38 (5), 669-672, 2017 | 46 | 2017 |
| Random variation analysis and variation-aware design of symmetric tunnel field-effect transistor H Lee, S Park, Y Lee, H Nam, C Shin IEEE Transactions on Electron Devices 62 (6), 1778-1783, 2014 | 29 | 2014 |
| Performance Booster for Vertical Tunnel Field-Effect Transistor: Field-Enhanced High- Layer H Lee, JD Park, C Shin IEEE Electron Device Letters 37 (11), 1383-1386, 2016 | 19 | 2016 |
| Random dopant fluctuation-induced threshold voltage variation-immune Ge FinFET with metal–interlayer–semiconductor source/drain C Shin, JK Kim, GS Kim, H Lee, C Shin, JK Kim, BJ Cho, HY Yu ieee transactions on electron devices 63 (11), 4167-4172, 2016 | 17 | 2016 |
| Analysis of random variations and variation-robust advanced device structures H Nam, GS Lee, H Lee, IJ Park, C Shin JSTS: Journal of Semiconductor Technology and Science 14 (1), 8-22, 2014 | 17 | 2014 |
| Design for variation-immunity in sub-10-nm stacked-nanowire FETs to suppress LER-induced random variations J Park, H Lee, S Oh, C Shin IEEE Transactions on Electron Devices 63 (12), 5048-5054, 2016 | 15 | 2016 |
| Transconductance amplification by the negative capacitance in ferroelectric-gated P3HT thin-film transistor J Jo, MG Kim, H Lee, H Choi, C Shin IEEE Transactions on Electron Devices 64 (12), 4974-4979, 2017 | 8 | 2017 |
| Simulation of negative capacitance based on the Miller model: Beyond the limitation of the Landau model H Lee, Y Yoon IEEE Transactions on Electron Devices 69 (1), 237-241, 2021 | 7 | 2021 |
| Experimental evidence of negative quantum capacitance in topological insulator for sub-60-mV/decade steep switching device H Choi, H Lee, J Park, HY Yu, TG Kim, C Shin Applied Physics Letters 109 (20), 2016 | 6 | 2016 |
| Worst case sampling method with confidence ellipse for estimating the impact of random variation on static random access memory (SRAM) S Oh, J Jo, H Lee, GS Lee, JD Park, C Shin JSTS: Journal of Semiconductor Technology and Science 15 (3), 374-380, 2015 | 5 | 2015 |
| A computational framework for gradually switching ferroelectric-based negative capacitance field-effect transistors H Lee, M Sritharan, Y Yoon IEEE Transactions on Electron Devices 69 (10), 5928-5933, 2022 | 4 | 2022 |
| Design considerations for engineering negative capacitance FET through multilayered channel and / double-gate stacks: an ab initio and NEGF … M Sritharan, H Lee, RKA Bennett, Y Yoon Journal of Computational Electronics 22 (5), 1338-1349, 2023 | 1 | 2023 |
| Modeling of hysteretic jump points in ferroelectric MOS capacitors H Lee, Y Yoon IEEE Transactions on Electron Devices 66 (7), 3093-3098, 2019 | 1 | 2019 |
| Assessing the Role of Dielectric Phase Defects in Doped Ferroelectric HfO2 Integrated in Negative Capacitance Field-Effect Transistors M Sritharan, H Lee, Y Yoon 2023 IEEE 23rd International Conference on Nanotechnology (NANO), 305-310, 2023 | | 2023 |
