| Caffeinated FPGAs: FPGA framework for convolutional neural networks R DiCecco, G Lacey, J Vasiljevic, P Chow, G Taylor, S Areibi 2016 International Conference on Field-Programmable Technology (FPT), 265-268, 2016 | 150 | 2016 |
| DLA: Compiler and FPGA overlay for neural network inference acceleration MS Abdelfattah, D Han, A Bitar, R DiCecco, S O'Connell, N Shanker, ... 2018 28th international conference on field programmable logic and …, 2018 | 104 | 2018 |
| FPGA-based training of convolutional neural networks with a reduced precision floating-point library R DiCecco, L Sun, P Chow 2017 International Conference on Field Programmable Technology (ICFPT), 239-242, 2017 | 31 | 2017 |
| A software-defined tensor streaming multiprocessor for large-scale machine learning D Abts, G Kimmell, A Ling, J Kim, M Boyd, A Bitar, S Parmar, I Ahmed, ... Proceedings of the 49th Annual International Symposium on Computer …, 2022 | 17 | 2022 |
| Inter-kernel links for direct inter-FPGA communication SM Balle, M Tetreault, R Dicecco Intel White Paper (WP-01305–1.0), 2020 | 4 | 2020 |
| Harnessing numerical flexibility for deep learning on fpgas AC Ling, MS Abdelfattah, S O'Connell, A Bitar, D Han, R Dicecco, ... Proceedings of the 9th International Symposium on Highly-Efficient …, 2018 | 2 | 2018 |
| Test considerations for jitter tolerance of wireline receivers R DiCecco, R Pahuta, C Holdenried, S Sadr 2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering …, 2014 | 2 | 2014 |
| Floating-point decomposition circuitry with dynamic precision R DiCecco, J Fender, S O'connell US Patent App. 16/818,889, 2020 | 1 | 2020 |
| Caffeinated FPGAs: FPGA Framework for Training and Inference of Convolutional Neural Networks With Reduced Precision Floating-Point Arithmetic R DiCecco University of Toronto (Canada), 2018 | | 2018 |
