| Reducing register ports for higher speed and lower energy I Park, MD Powell, TN Vijaykumar 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002 | 212 | 2002 |
| Reducing design complexity of the load/store queue I Park, CL Ooi, TN Vijaykumar Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 152 | 2003 |
| Newton: A DRAM-maker’s accelerator-in-memory (AiM) architecture for machine learning M He, C Song, I Kim, C Jeong, S Kim, I Park, M Thottethodi, ... 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 121 | 2020 |
| Implicitly-multithreaded processors I Park, B Falsafi, TN Vijaykumar ACM SIGARCH Computer Architecture News 31 (2), 39-51, 2003 | 77 | 2003 |
| A 1ynm 1.25 V 8Gb, 16Gb/s/pin GDDR6-based accelerator-in-memory supporting 1TFLOPS MAC operation and various activation functions for deep-learning applications S Lee, K Kim, S Oh, J Park, G Hong, D Ka, K Hwang, J Park, K Kang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 74 | 2022 |
| Branch target prediction for multi-target branches by identifying a repeated pattern I Park, PC Pattnaik, JD Choi US Patent 7,409,535, 2008 | 63 | 2008 |
| Multiplex: Unifying conventional and speculative thread-level parallelism on a chip multiprocessor CL Ooi, SW Kim, I Park, R Eigenmann, B Falsafi, TN Vijaykumar Proceedings of the 15th international conference on Supercomputing, 368-380, 2001 | 62 | 2001 |
| Register Checkpointing for Speculative Modes of Execution in Out-of-Order Processors HW Cain III, K Ekanadham, I Park US Patent App. 12/729,282, 2011 | 35 | 2011 |
| Enhancing timeliness of cache prefetching K Ekanadham, JA Navarro, I Park, CLK Shum US Patent 8,285,941, 2012 | 26 | 2012 |
| Memory systems having extended product lifetime and methods of operating the same B Jinho, I Park, S Da Eun, LEE Hokyoon, JOO Youngpyo US Patent 10,459,794, 2019 | 23 | 2019 |
| Silent-PIM: Realizing the processing-in-memory computing with standard memory requests CH Kim, WJ Lee, Y Paik, K Kwon, SY Kim, I Park, SW Kim IEEE Transactions on Parallel and Distributed Systems 33 (2), 251-262, 2021 | 20 | 2021 |
| Design of processing-“inside”-memory optimized for dram behaviors WJ Lee, CH Kim, Y Paik, J Park, I Park, SW Kim IEEE Access 7, 82633-82648, 2019 | 20 | 2019 |
| Operating a stack of information in an information handling system K Ekanadham, BR Konigsburg, DS Levitan, JE Moreira, D Mui, I Park US Patent 8,943,299, 2015 | 20 | 2015 |
| System architecture and software stack for GDDR6-AiM Y Kwon, K Vladimir, N Kim, W Shin, J Won, M Lee, H Joo, H Choi, G Kim, ... 2022 IEEE Hot Chips 34 Symposium (HCS), 1-25, 2022 | 16 | 2022 |
| Memory device and system including on chip ECC circuit JH Baek, JR Kim, I Park, HK Lee US Patent 10,061,642, 2018 | 9 | 2018 |
| Multiprocessor system and method for managing cache memory thereof I Park, YP Joo US Patent 9,183,149, 2015 | 8 | 2015 |
| Memory controller and memory system including the same I Park, SJ Byeon, TS Song US Patent 10,318,187, 2019 | 7 | 2019 |
| Prefetching indirect array accesses K Ekanadham, I Park, SR Seelam US Patent 7,539,844, 2009 | 6 | 2009 |
| Branch target prediction for multi-target branches by identifying a repeated pattern I Park, PC Pattnaik, JD Choi US Patent App. 12/183,995, 2008 | 5 | 2008 |
| Multiplex: Unifying conventional and speculative thread-level parallelism on a chip multiprocessor SW Kim, CL Ooi, I Park, R Eigenmann, B Falsafi, TN Vijaykumar ECE Technical Reports, 29, 2000 | 4 | 2000 |
