| Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019 | 75 | 2019 |
| Fabricating large area multi-tier nanostructures SV Sreenivasan, P Joseph, O Abed, M Grigas, A Mallavarapu, P Ajay US Patent 9,941,389, 2018 | 25 | 2018 |
| Inverse tone direct print EUV lithography enabled by selective material deposition P Joseph, EA De Silva, FL LIE, SA Sieg, Y Mignot, I Seshadri US Patent 10,304,744, 2019 | 20* | 2019 |
| Scatterometry for nanoimprint lithography R Zhu, SRJ Brueck, N Dawson, T Busani, P Joseph, S Singhal, ... Journal of Vacuum Science & Technology B 34 (6), 06K503, 2016 | 19 | 2016 |
| Nanoscale limits of angular optical scatterometry R Zhu, JJ Faria-Briceno, SRJ Brueck, P Joseph, S Singhal, ... AIP Advances 10 (1), 2020 | 8 | 2020 |
| Fabrication of self-aligned multilevel nanostructures P Joseph, S Singhal, O Abed, SV Sreenivasan Microelectronic Engineering 169 (C), 49–61, 2016 | 4 | 2016 |
| Semiconductor structure with fully aligned vias EA De Silva, A Dutta, P Joseph, N Felix US Patent 11,302,573, 2022 | 2 | 2022 |
| Staggered stacked vertical crystalline semiconducting channels K Tsung-Sheng, T Li, A Rahman, P Joseph, I Seshadri, EA De Silva US Patent 11,251,182, 2022 | 1 | 2022 |
| Inverse tone pillar printing method using polymer brush grafts N Felix, EA De Silva, P Joseph, A Dutta US Patent 11,133,195, 2021 | 1 | 2021 |
| Vertically stacked fin semiconductor devices P Joseph, T Li, I Seshadri, EA De Silva US Patent 11,075,266, 2021 | 1 | 2021 |
| Semiconductor device with multiple threshold voltages P Joseph, I Seshadri, EA De Silva US Patent 10,665,461, 2020 | 1 | 2020 |
| Hard mask replenishment for etching processes P Joseph, EA De Silva US Patent App. 16/175,032, 2020 | 1 | 2020 |
| A comparative analysis of EUV sheet and gate patterning for beyond 7nm gate all around stacked nanosheet FET’s (Conference Presentation) I Seshadri, P Joseph, SA Sieg, T Li, W Xu, E Miller, DJ Dechene, ... Design-Process-Technology Co-optimization for Manufacturability XIV 11328 …, 2020 | 1 | 2020 |
| Transistor having wrap-around source/drain contacts and under-contact spacers Y Song, P Joseph, A Greene, K Cheng US Patent 11,876,136, 2024 | | 2024 |
| Staggered stacked vertical crystalline semiconducting channels K Tsung-Sheng, T Li, A Rahman, P Joseph, I Seshadri, EA De Silva US Patent 11,756,961, 2023 | | 2023 |
| Inverse tone pillar printing method using organic planarizing layer pillars N Felix, EA De Silva, P Joseph, A Dutta US Patent 11,699,592, 2023 | | 2023 |
| AIRGAP ISOLATION FOR BACK-END-OF-THE-LINE SEMICONDUCTOR INTERCONNECT STRUCTURE WITH TOP VIA A Dutta, EA De Silva, P Joseph, J Church US Patent App. 17/449,381, 2023 | | 2023 |
| Dielectric structure to prevent hard mask erosion T Li, EA De Silva, K Tsung-Sheng, P Joseph US Patent 11,562,908, 2023 | | 2023 |
| Bilayer hardmask for direct print lithography P Joseph, G Karve, Y Mignot US Patent 11,398,377, 2022 | | 2022 |
| Transistor having wrap-around source/drain contacts and under-contact spacers Y Song, P Joseph, A Greene, K Cheng US Patent 11,296,226, 2022 | | 2022 |
S.V. SreenivasanUniversity of Texas at AustinVerified email at mail.utexas.edu
