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Dengquan Li (李登全)
Dengquan Li (李登全)
Verified email at xidian.edu.cn - Homepage
Title
Cited by
Cited by
Year
A 1.4-mW 10-bit 150-MS/s SAR ADC with nonbinary split capacitive DAC in 65-nm CMOS
D Li, Z Zhu, R Ding, Y Yang
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (11), 1524-1528, 2017
412017
27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering
J Liu, D Li, Y Zhong, X Tang, N Sun
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 369-371, 2021
352021
A 10-bit 600-MS/s time-interleaved SAR ADC with interpolation-based timing skew calibration
D Li, Z Zhu, R Ding, M Liu, Y Yang, N Sun
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (1), 16-20, 2018
322018
A 7-bit 900-MS/s 2-then-3-bit/cycle SAR ADC with background offset calibration
D Li, Z Zhu, J Liu, H Zhuang, Y Yang, N Sun
IEEE Journal of Solid-State Circuits 55 (11), 3051-3063, 2020
252020
A 10-kS/s 625-Hz-bandwidth 65-dB SNDR second-order noise-shaping SAR ADC for biomedical sensor applications
J Hu, D Li, M Liu, Z Zhu
IEEE Sensors Journal 20 (23), 13881-13891, 2019
222019
An 8-Bit 2.1-mW 350-MS/s SAR ADC with 1.5 b/cycle Redundancy in 65-nm CMOS
D Li, M Liu, L Zhao, H Mao, R Ding, Z Zhu
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (11), 2307-2311, 2020
212020
A background fast convergence algorithm for timing skew in time-interleaved ADCs
D Li, Z Zhu, L Zhang, Y Yang
Microelectronics Journal 47, 45-52, 2016
182016
A 7b 2.6 mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration
D Li, J Liu, H Zhuang, Z Zhu, Y Yang, N Sun
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
142019
A 10-bit 100-ms/s 5.23-mw sar adc in 0.18-μm cmos
R Ma, L Wang, D Li, R Ding, Z Zhu
Microelectronics Journal 78, 63-72, 2018
142018
A 0.6-V 94-nW 10-bit 200-kS/s single-ended SAR ADC for implantable biosensor applications
X Zhao, D Li, X Zhang, S Liu, Z Zhu
IEEE Sensors Journal 22 (18), 17904-17913, 2022
112022
A dual-supply two-stage CMOS op-amp for high-speed pipeline ADCs application
M Liu, D Li, Z Zhu
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (4), 650-654, 2019
112019
Radio frequency analog-to-digital converters: Systems and circuits review
D Li, X Zhao, S Liu, M Liu, R Ding, Y Liang, Z Zhu
Microelectronics Journal 119, 105331, 2022
102022
An 8-bit 0.333–2 GS/s configurable time-interleaved SAR ADC in 65-nm CMOS
D Li, L Zhang, Z Zhu, Y Yang
Journal of Circuits, Systems and Computers 24 (06), 1550093, 2015
92015
A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique
L Yuhua, Z Zirui, LIU Shubin, LI Dengquan, D Ruixue, ZHU Zhangming
Chinese Journal of Electronics 30 (5), 853-860, 2021
82021
A 10-bit 2.5-GS/s two-step ADC with selective time-domain quantization in 28-nm CMOS
M Liu, C Zhang, S Liu, D Li
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (3), 1091-1101, 2021
72021
A TD-ADC for IR-UWB radars with equivalent sampling technology and 8-GS/s effective sampling rate
Z Zhu, Y Zhu, D Li, M Liu
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (3), 888-892, 2020
72020
A fast convergence second-order compensation for timing skew in time-interleaved ADCs
D Li, L Zhao, L Wang, Y Shen, Z Zhu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (10 …, 2022
62022
A background timing skew calibration technique in time-interleaved ADCs with second order compensation
D Li, R Ding, Z Zhu, Y Yang
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 53-56, 2018
62018
A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16 Time-Domain Interpolation in 28-nm CMOS
D Li, X Zhao, Y Shen, S Liu, Z Zhu
IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
42023
A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS
H Mao, D Li, S Liu
Microelectronics Journal 122, 105395, 2022
42022
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