‪Chirag Desai‬ - ‪Google Scholar‬

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Cited by

	All	Since 2019
Citations	94	90
h-index	2	2
i10-index	2	2

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24

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20182019202020212022202320243 8 14 18 23 23 4

Co-authors

Bertan Bakkalogluarizona state university, texas instrumentsVerified email at asu.edu
Sayfe KiaeiProfessor, School of Electrical, Computer and Energy EngineeringVerified email at asu.edu
Debashis MandalAssistant Professor, Department of Electrical Engineering, Indian Institute of Technology KharagpurVerified email at ee.iitkgp.ac.in

Chirag Desai

Chirag Desai

PMIC Design Engineer

Verified email at meta.com

Power-management IC Design Analog & Mixed-Signal Circuits Design


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Adaptively biased output cap-less NMOS LDO with 19 ns settling time D Mandal, C Desai, B Bakkaloglu, S Kiaei IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2), 167-171, 2018	57	2018
A 1.66 mV FOM output cap-less LDO with current-reused dynamic biasing and 20 ns settling time C Desai, D Mandal, B Bakkaloglu, S Kiaei IEEE Solid-State Circuits Letters 1 (2), 50-53, 2018	37	2018
Wide Input Common-mode Range Fully Integrated Low-dropout Voltage Regulators C Desai Arizona State University, 2016		2016

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