| Deep convolutional neural network architecture with reconfigurable computation patterns F Tu, S Yin, P Ouyang, S Tang, L Liu, S Wei IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 340 | 2017 |
| A high energy efficient reconfigurable hybrid neural network processor for deep learning applications S Yin, P Ouyang, S Tang, F Tu, X Li, S Zheng, T Lu, J Gu, L Liu, S Wei IEEE Journal of Solid-State Circuits 53 (4), 968-982, 2017 | 222 | 2017 |
| A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications S Yin, P Ouyang, S Tang, F Tu, X Li, L Liu, S Wei 2017 Symposium on VLSI Circuits, C26-C27, 2017 | 105 | 2017 |
| RANA: Towards efficient neural acceleration with refresh-optimized embedded DRAM F Tu, W Wu, S Yin, L Liu, S Wei 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 86 | 2018 |
| A 28nm 29.2 TFLOPS/W BF16 and 36.5 TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep … F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 254-256, 2022 | 83 | 2022 |
| Dota: detect and omit weak attentions for scalable transformer acceleration Z Qu, L Liu, F Tu, Z Chen, Y Ding, Y Xie Proceedings of the 27th ACM International Conference on Architectural …, 2022 | 66 | 2022 |
| Evolver: A deep learning processor with on-device quantization–voltage–frequency tuning F Tu, W Wu, Y Wang, H Chen, F Xiong, M Shi, N Li, J Deng, T Chen, L Liu, ... IEEE Journal of Solid-State Circuits 56 (2), 658-673, 2020 | 59 | 2020 |
| GNA: Reconfigurable and efficient architecture for generative network acceleration J Yan, S Yin, F Tu, L Liu, S Wei IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 51 | 2018 |
| A high throughput acceleration for hybrid neural networks with efficient resource management on FPGA S Yin, S Tang, X Lin, P Ouyang, F Tu, L Liu, S Wei IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 51 | 2018 |
| A 28nm 15.59 µJ/token full-digital bitline-transpose CIM-based sparse transformer accelerator with pipeline/parallel reconfigurable modes F Tu, Z Wu, Y Wang, L Liang, L Liu, Y Ding, L Liu, S Wei, Y Xie, S Yin 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 466-468, 2022 | 44 | 2022 |
| AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs S Tang, S Yin, S Zheng, P Ouyang, F Tu, L Yao, JZ Wu, W Cheng, L Liu, ... 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA …, 2017 | 42 | 2017 |
| An energy efficient jpeg encoder with neural network based approximation and near-threshold computing Z Wang, S Yin, F Tu, L Liu, S Wei 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 39 | 2018 |
| LCP: A layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA X Lin, S Yin, F Tu, L Liu, X Li, S Wei Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 36 | 2018 |
| H2learn: High-efficiency learning accelerator for high-accuracy spiking neural networks L Liang, Z Qu, Z Chen, F Tu, Y Wu, L Deng, G Li, P Li, Y Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 33 | 2021 |
| ReDCIM: Reconfigurable digital computing-in-memory processor with unified FP/INT pipeline for cloud AI acceleration F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin IEEE Journal of Solid-State Circuits 58 (1), 243-255, 2022 | 29 | 2022 |
| Duet: Boosting deep neural network efficiency on dual-module architecture L Liu, Z Qu, L Deng, F Tu, S Li, X Hu, Z Gu, Y Ding, Y Xie 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 29 | 2020 |
| TranCIM: Full-digital bitline-transpose CIM-based sparse transformer accelerator with pipeline/parallel reconfigurable modes F Tu, Z Wu, Y Wang, L Liang, L Liu, Y Ding, L Liu, S Wei, Y Xie, S Yin IEEE Journal of Solid-State Circuits 58 (6), 1798-1809, 2022 | 25 | 2022 |
| INSPIRE: in-storage private information retrieval via protocol and architecture co-design J Lin, L Liang, Z Qu, I Ahmad, L Liu, F Tu, T Gupta, Y Ding, Y Xie Proceedings of the 49th Annual International Symposium on Computer …, 2022 | 24 | 2022 |
| Parana: A parallel neural architecture considering thermal problem of 3d stacked memory S Yin, S Tang, X Lin, P Ouyang, F Tu, J Zhao, C Xu, S Li, Y Xie, SJ Wei IEEE Transactions on Parallel and Distributed Systems 30 (1), 146-160, 2018 | 20 | 2018 |
| 16.1 MuITCIM: A 28nm /Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers F Tu, Z Wu, Y Wang, W Wu, L Liu, Y Hu, S Wei, S Yin 2023 IEEE International Solid-State Circuits Conference (ISSCC), 248-250, 2023 | 19 | 2023 |
Shouyi YinTsinghua University在 tsinghua.edu.cn 的电子邮件经过验证
