| Advances, challenges and opportunities in 3D CMOS sequential integration P Batude, M Vinet, B Previtali, C Tabone, C Xu, J Mazurier, O Weber, ... 2011 International Electron Devices Meeting, 7.3. 1-7.3. 4, 2011 | 383 | 2011 |
| Advances in 3D CMOS sequential integration P Batude, M Vinet, A Pouydebasque, C Le Royer, B Previtali, C Tabone, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 363 | 2009 |
| Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance F Mayer, C Le Royer, JF Damlencourt, K Romanjek, F Andrieu, C Tabone, ... 2008 IEEE International Electron Devices Meeting, 1-5, 2008 | 363 | 2008 |
| Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond O Faynot, F Andrieu, O Weber, C Fenouillet-Béranger, P Perreau, ... 2010 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2010 | 306 | 2010 |
| 3D monolithic integration: Technological challenges and electrical results M Vinet, P Batude, C Tabone, B Previtali, C LeRoyer, A Pouydebasque, ... Microelectronic Engineering 88 (4), 331-335, 2011 | 293 | 2011 |
| Engineered substrates for future More Moore and More than Moore integrated devices L Clavelier, C Deguet, L Di Cioccio, E Augendre, A Brugere, P Gueguen, ... 2010 International Electron Devices Meeting, 2.6. 1-2.6. 4, 2010 | 250 | 2010 |
| Novel integration process and performances analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with Metal/High-K Gate stack E Bernard, T Ernst, B Guillaumot, N Vulliet, V Barral, V Maffini-Alvaro, ... 2008 Symposium on VLSI Technology, 16-17, 2008 | 236 | 2008 |
| 3D monolithic integration P Batude, M Vinet, A Pouydebasque, C Le Royer, B Previtali, C Tabone, ... 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2233-2236, 2011 | 235 | 2011 |
| High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding O Weber, O Faynot, F Andrieu, C Buj-Dufournet, F Allain, P Scheiblin, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 215 | 2008 |
| 15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET C Dupré, A Hubert, S Becu, M Jublot, V Maffini-Alvaro, C Vizioz, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 194 | 2008 |
| Lateral interband tunneling transistor in silicon-on-insulator C Aydin, A Zaslavsky, S Luryi, S Cristoloveanu, D Mariolle, D Fraboulet, ... Applied Physics Letters 84 (10), 1780-1782, 2004 | 183 | 2004 |
| FDSOI devices with thin BOX and ground plane integration for 32 nm node and below C Fenouillet-Beranger, S Denorme, P Perreau, C Buj, O Faynot, F Andrieu, ... Solid-State Electronics 53 (7), 730-734, 2009 | 163 | 2009 |
| Multiple gate devices: advantages and challenges T Poiroux, M Vinet, O Faynot, J Widiez, J Lolivier, T Ernst, B Previtali, ... Microelectronic Engineering 80, 378-385, 2005 | 155 | 2005 |
| Bonded planar double-metal-gate NMOS transistors down to 10 nm M Vinet, T Poiroux, J Widiez, J Lolivier, B Previtali, C Vizioz, B Guillaumot, ... IEEE Electron Device Letters 26 (5), 317-319, 2005 | 147 | 2005 |
| 75 nm damascene metal gate and high-k integration for advanced CMOS devices B Guillaumot, X Garros, F Lime, K Oshima, B Tavel, JA Chroboczek, ... Digest. International Electron Devices Meeting,, 355-358, 2002 | 143 | 2002 |
| Simple and controlled single electron transistor based on doping modulation in silicon nanowires M Hofheinz, X Jehl, M Sanquer, G Molas, M Vinet, S Deleonibus Applied physics letters 89 (14), 2006 | 128 | 2006 |
| How far will silicon nanocrystals push the scaling limits of NVMs technologies? B De Salvo, C Gerardi, S Lombardo, T Baron, L Perniola, D Mariolle, ... IEEE International Electron Devices Meeting 2003, 26.1. 1-26.1. 4, 2003 | 116 | 2003 |
| Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS) B De Salvo, C Gerardi, R van Schaijk, SA Lombardo, D Corso, ... IEEE Transactions on Device and Materials Reliability 4 (3), 377-389, 2004 | 104 | 2004 |
| Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance J Widiez, J Lolivier, M Vinet, T Poiroux, B Previtali, F Daugé, M Mouis, ... IEEE Transactions on Electron Devices 52 (8), 1772-1779, 2005 | 103 | 2005 |
| Size dependence of surface-roughness-limited mobility in silicon-nanowire FETs S Poli, MG Pala, T Poiroux, S Deleonibus, G Baccarani IEEE Transactions on Electron Devices 55 (11), 2968-2976, 2008 | 100 | 2008 |
