| Machine learning and deep learning frameworks and libraries for large-scale data mining: a survey G Nguyen, S Dlugolinsky, M Bobák, V Tran, Á López García, I Heredia, ... Artificial Intelligence Review 52, 77-124, 2019 | 775 | 2019 |
| High throughput floating point exponential function implemented in FPGA P Malík 2015 IEEE Computer Society Annual Symposium on VLSI, 97-100, 2015 | 19 | 2015 |
| High throughput floating-point dividers implemented in FPGA P Malik 2015 IEEE 18th International Symposium on Design and Diagnostics of …, 2015 | 19 | 2015 |
| Instance segmentation model created from three semantic segmentations of mask, boundary and centroid pixels verified on GlaS dataset P Malík, Š Krištofík, K Knapová 2020 15th Conference on computer science and information systems (FedCSIS …, 2020 | 11 | 2020 |
| System and method for handling parallel updates of objects requiring time sensitive acknowledgement AW Daum, B Ernesti, R Colle, T Griesser, H Saterdag, D Zoch, L Lu, ... US Patent 7,689,561, 2010 | 8 | 2010 |
| Clockless Implementation of LEON2 for Low-Power Applications M Simlastik, V Stopjakova, L Majer, P Malik 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-4, 2007 | 8 | 2007 |
| MDCT/IMDCT low power implementations in 90 nm CMOS technology for MP3 audio P Malik, M Ufnal, AW Luczyk, M Balaz, WA Pleskacz 2009 12th International Symposium on Design and Diagnostics of Electronic …, 2009 | 7 | 2009 |
| Universal framework for remote firmware updates of low-power devices O Kachman, M Balaz, P Malik Computer Communications 139, 91-102, 2019 | 6 | 2019 |
| MDCT IP Core Generator with Architectural Model Simulation P Malik, M Balaz, T Pikula, M Simlastik 2006 IFIP International Conference on Very Large Scale Integration, 18-23, 2006 | 5 | 2006 |
| Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement Š Krištofík, M Baláž, P Malík Microelectronics Reliability 86, 38-53, 2018 | 4 | 2018 |
| Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults Š Krištofík, P Malík Integration 62, 190-204, 2018 | 4 | 2018 |
| Dedicated hardware architecture for object tracking preprocessing implemented in FPGA P Malík 17th International Symposium on Design and Diagnostics of Electronic …, 2014 | 4 | 2014 |
| Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC P Malík IET Circuits, Devices & Systems 5 (5), 351-359, 2011 | 4 | 2011 |
| A generic IP core of the identical forward and inverse 12/36-point MDCT architecture and an architectural model simulation toolbox P Malik 2007 14th IEEE International Conference on Electronics, Circuits and Systems …, 2007 | 4 | 2007 |
| FPGA implementation of fully parallel fast MDCT algorithm M Pohronska, P Malik, M Balaz IEEE EUROCON 2009, 161-166, 2009 | 3 | 2009 |
| Natural logarithm and division floating-point high throughput co-processor implemented in FPGA P Malik 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 1-6, 2016 | 2 | 2016 |
| Hardware architecture dedicated for arithmetic mean filtration implemented in FPGA P Malík 2013 8th International Conference on Computer Engineering & Systems (ICCES …, 2013 | 2 | 2013 |
| System and method for handling parallel updates of objects requiring time sensitive acknowledgement AW Daum, B Ernesti, R Colle, T Griesser, H Saterdag, D Zoch, L Lu, ... US Patent 7,890,462, 2011 | 2 | 2011 |
| Various MDCT implementations in 0.35 μ CMOS P Malik, M Balaz, M Simlastik, A Luczyk, W Pleskacz 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008 | 2 | 2008 |
| An Improved MDCT IP Core Generator with Architectural Model Simulation P Malik, M Balaz, T Pikula, M Simlastik 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-6, 2007 | 2 | 2007 |
