| Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory X Dong, C Xu, Y Xie, NP Jouppi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 1367 | 2012 |
| A novel architecture of the 3D stacked MRAM L2 cache for CMPs G Sun, X Dong, Y Xie, J Li, Y Chen 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 538 | 2009 |
| Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement X Dong, X Wu, G Sun, Y Xie, H Li, Y Chen Proceedings of the 45th annual design automation conference, 554-559, 2008 | 429 | 2008 |
| Design implications of memristor-based RRAM cross-point structures C Xu, X Dong, NP Jouppi, Y Xie 2011 Design, Automation & Test in Europe, 1-6, 2011 | 318 | 2011 |
| System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs) X Dong, Y Xie 2009 Asia and South Pacific Design Automation Conference, 234-241, 2009 | 220 | 2009 |
| Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems X Dong, N Muralimanohar, N Jouppi, R Kaufmann, Y Xie Proceedings of the conference on high performance computing networking …, 2009 | 208 | 2009 |
| Energy-and endurance-aware design of phase change memory caches Y Joo, D Niu, X Dong, G Sun, N Chang, Y Xie 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 197 | 2010 |
| Simple but effective heterogeneous main memory with on-chip memory controller support X Dong, Y Xie, N Muralimanohar, NP Jouppi SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010 | 188 | 2010 |
| i2WAP: Improving Non-Volatile Cache Lifetime by Reducing Inter-and Intra-Set Write Variations J Wang, X Dong, Y Xie, NP Jouppi International Symposium on High Performance Computer Architecture, 2013, 2013 | 160 | 2013 |
| PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM X Dong, NP Jouppi, Y Xie Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 137 | 2009 |
| Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs AK Mishra, X Dong, G Sun, Y Xie, N Vijaykrishnan, CR Das ACM SIGARCH Computer Architecture News 39 (3), 69-80, 2011 | 133 | 2011 |
| AdaMS: Adaptive MLC/SLC phase-change memory design for file storage X Dong, Y Xie 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 31-36, 2011 | 108 | 2011 |
| Fabrication cost analysis and cost-aware design space exploration for 3-D ICs X Dong, J Zhao, Y Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 104 | 2010 |
| OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches J Wang, X Dong, Y Xie Design, Automation & Test in Europe, 2013 | 84 | 2013 |
| Hybrid checkpointing using emerging nonvolatile memories for future exascale systems X Dong, Y Xie, N Muralimanohar, NP Jouppi ACM Transactions on Architecture and Code Optimization (TACO) 8 (2), 1-29, 2011 | 84 | 2011 |
| Energy-efficient multi-level cell phase-change memory system with data encoding J Wang, X Dong, G Sun, D Niu, Y Xie 2011 IEEE 29th International Conference on Computer Design (ICCD), 175-182, 2011 | 81 | 2011 |
| Kernel masking of DRAM defects DT Chun, Y Li, X Dong, J Suh, JP Kim, DV Sriramagiri US Patent 9,299,457, 2016 | 53 | 2016 |
| DRAM sub-array level autonomic refresh memory controller optimization DV Sriramagiri, J Suh, X Dong US Patent 9,524,771, 2016 | 51 | 2016 |
| 3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis A Al Maashri, G Sun, X Dong, V Narayanan, Y Xie 2009 IEEE International Conference on Computer Design, 254-259, 2009 | 49 | 2009 |
| Method and apparatus for refreshing a memory cell DV Sriramagiri, JP Kim, J Suh, X Dong US Patent 9,911,485, 2018 | 43 | 2018 |
Yuan XieChair Professor of Hong Kong University of Science and Technology (HKUST)Verified email at ust.hk
