Source/drain eSiGe engineering for FinFET technology J Peng, Y Qi, HC Lo, P Zhao, C Yong, J Yan, X Dou, H Zhan, Y Shen, ... Semiconductor Science and Technology 32 (9), 094004, 2017 | 13 | 2017 |
Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure X Zhang, OS Kwon, J Yan, WH Hung, R Miller, H Shen US Patent 9,159,667, 2015 | 11 | 2015 |
Elimination of tungsten-voids in middle-of-line contacts for advanced planar cmos and finfet technology WP Peng, M Chi, G Derderian, K Das, Y Zhang, JB Laloe, D Deniz, S Patil, ... 2016 China Semiconductor Technology International Conference (CSTIC), 1-4, 2016 | 6 | 2016 |
Dual-curvature cavity for epitaxial semiconductor growth A Vinslava, HC Lo, Y Shi, P Jianwei, J Yan, Y Qi US Patent 10,297,675, 2019 | 4 | 2019 |
Trade-off between gate oxide integrity and transistor performance for FinFET technology HC Lo, J Peng, C Yong, S Uppal, Y Qi, H Zhan, YP Shen, X Chen, J Yan, ... ECS Journal of Solid State Science and Technology 6 (8), N137, 2017 | 4 | 2017 |
Dual-curvature cavity for epitaxial semiconductor growth A Vinslava, HC Lo, Y Shi, P Jianwei, J Yan, Y Qi US Patent App. 16/276,045, 2019 | 1 | 2019 |
E-fuse structure for an integrated circuit product X Zhang, OS Kwon, J Yan, WH Hung, R Miller, H Shen US Patent App. 14/817,546, 2015 | | 2015 |
Trade-Off between Gate Oxide Integrity and Transistor Performance for FinFET Technology J Peng, S Uppal, Y Qi, H Zhan, YP Shen, X Chen, J Yan, B Zhu, S Shintri, ... | | |