| Computer architecture: a quantitative approach JL Hennessy, DA Patterson Elsevier, 2011 | 16853 | 2011 |
| Computer organization and design ARM edition: the hardware software interface DA Patterson, JL Hennessy Morgan kaufmann, 2016 | 5370 | 2016 |
| Computer architecture: a quantitative approach DA Patterson, JL Hennessy, D Goldberg Morgan Kaufmann, 1990 | 2530 | 1990 |
| Memory consistency and event ordering in scalable shared-memory multiprocessors K Gharachorloo, D Lenoski, J Laudon, P Gibbons, A Gupta, J Hennessy ACM SIGARCH Computer Architecture News 18 (2SI), 15-26, 1990 | 1716 | 1990 |
| The stanford dash multiprocessor D Lenoski, J Laudon, K Gharachorloo, WD Weber, A Gupta, J Hennessy, ... Computer 25 (3), 63-79, 1992 | 1438 | 1992 |
| The stanford flash multiprocessor J Kuskin, D Ofelt, M Heinrich, J Heinlein, R Simoni, K Gharachorloo, ... Proceedings of 21 International Symposium on Computer Architecture, 302-313, 1994 | 1057 | 1994 |
| The directory-based cache coherence protocol for the DASH multiprocessor D Lenoski, J Laudon, K Gharachorloo, A Gupta, J Hennessy ACM SIGARCH Computer Architecture News 18 (2SI), 148-159, 1990 | 972 | 1990 |
| An evaluation of directory schemes for cache coherence A Agarwal, R Simoni, J Hennessy, M Horowitz ACM SIGARCH Computer Architecture News 16 (2), 280-298, 1988 | 834 | 1988 |
| SUIF: An infrastructure for research on parallelizing and optimizing compilers RP Wilson, RS French, CS Wilson, SP Amarasinghe, JM Anderson, ... ACM Sigplan Notices 29 (12), 31-37, 1994 | 758 | 1994 |
| The priority-based coloring approach to register allocation FC Chow, JL Hennessy ACM Transactions on Programming Languages and Systems (TOPLAS) 12 (4), 501-536, 1990 | 511 | 1990 |
| An analytical cache model A Agarwal, J Hennessy, M Horowitz ACM Transactions on Computer Systems (TOCS) 7 (2), 184-215, 1989 | 446 | 1989 |
| Cache performance of operating system and multiprogramming workloads A Agarwal, J Hennessy, M Horowitz ACM Transactions on Computer Systems (TOCS) 6 (4), 393-431, 1988 | 372 | 1988 |
| Register allocation by priority-based coloring F Chow, J Hennessy Proceedings of the 1984 SIGPLAN symposium on Compiler construction, 222-232, 1984 | 352 | 1984 |
| Performance evaluation of memory consistency models for shared-memory multiprocessors K Gharachorloo, A Gupta, J Hennessy ACM SIGPLAN Notices 26 (4), 245-257, 1991 | 350 | 1991 |
| Load balancing and data locality in adaptive hierarchical N-body methods: Barnes-Hut, fast multipole, and radiosity JP Singh, C Holt, T Totsuka, A Gupta, J Hennessy Journal of Parallel and Distributed Computing 27 (2), 118-141, 1995 | 334 | 1995 |
| Postpass code optimization of pipeline constraints JL Hennessy, T Gross ACM Transactions on Programming Languages and Systems (TOPLAS) 5 (3), 422-448, 1983 | 334 | 1983 |
| Two techniques to enhance the performance of memory consistency models K Gharachorloo, A Gupta, JL Hennessy Computer Systems Laboratory, Stanford University, 1991 | 331 | 1991 |
| Efficient and exact data dependence analysis DE Maydan, JL Hennessy, MS Lam Proceedings of the ACM SIGPLAN 1991 conference on Programming language …, 1991 | 323 | 1991 |
| False sharing and spatial locality in multiprocessor caches J Torrellas, HS Lam, JL Hennessy IEEE Transactions on Computers 43 (6), 651-663, 1994 | 314 | 1994 |
| VLSI processor architecture JL Hennessy IEEE Transactions on Computers 33 (12), 1221-1246, 1984 | 313 | 1984 |
David PattersonProfessor of Computer Science, UC BerkeleyVerified email at cs.berkeley.edu
