| Vitruvius+: an area-efficient RISC-V decoupled vector coprocessor for high performance computing applications F Minervini, O Palomar, O Unsal, E Reggiani, J Quiroga, J Marimon, ... ACM Transactions on Architecture and Code Optimization 20 (2), 1-25, 2023 | 22 | 2023 |
| An academic risc-v silicon implementation based on open-source components J Abella, C Bulla, G Cabo, FJ Cazorla, A Cristal, M Doblas, R Figueras, ... 2020 XXXV conference on design of circuits and integrated systems (DCIS), 1-6, 2020 | 21 | 2020 |
| Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology M Doblas Font, G Candón Arenas, X Carril Gil, M Dominguez de la Rocha, ... 38th Conference on Design of Circuits and Integrated Systems (DCIS 2023 …, 2023 | | 2023 |
| DVINO: A RISC-V vector processor implemented in 65nm technology G Cabo Pitarch, G Candon, X Carril, M Doblas Font, ... DCIS 2022: proceedings of the 37th Conference on Design of Circuits and …, 2022 | | 2022 |
| Low Energy DRAM Controller for Computer Systems A González Trejo Universitat Politècnica de Catalunya, 2019 | | 2019 |
| Sistema embebido enfocado a exploración mediante un móvil aéreo A González Trejo González Trejo, Alberto, 0 | | |
| Lagarto: First Silicon RISC-V Academic Processor Developed in Spain J Abella, G Cabo, FJ Cazorla, A Cristal, R Figueras, A González, ... | | |
