Jiaojiao Ou
Jiaojiao Ou
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Design for manufacturability and reliability in extreme-scaling VLSI
B Yu, X Xu, S Roy, Y Lin, J Ou, DZ Pan
Science China Information Sciences 59, 1-23, 2016
New insights into AC RTN in scaled high-к/metal-gate MOSFETs under digital circuit operations
J Zou, R Wang, N Gong, R Huang, X Xu, J Ou, C Liu, J Wang, J Liu, J Wu, ...
2012 Symposium on VLSI Technology (VLSIT), 139-140, 2012
Concurrent Guiding Template Assignment and Redundant Via Insertion for DSA-MP Hybrid Lithography
J Ou, B Yu, DZ Pan
International Symposium on Physical Design, 2016
Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design
J Ou, B Yu, JR Gao, D Pan, M Preil, A Latypov
Directed self-assembly cut mask assignment for unidirectional design
J Ou, B Yu, JR Gao, D Pan
Journal of Micro/Nanolithography, MEMS, and MOEMS 14 (3), 2015
Machine learning for mask/wafer hotspot detection and mask synthesis
Y Lin, X Xu, J Ou, DZ Pan
Photomask Technology 2017 10451, 72-84, 2017
New observations on AC NBTI induced dynamic variability in scaled high-κ/metal-gate MOSFETs: characterization, origin of frequency dependence, and impacts on circuits
C Liu, P Ren, R Wang, R Huang, J Ou, Q Huang, J Zou, J Wang, J Wu, ...
2012 International Electron Devices Meeting, 19.5. 1-19.5. 4, 2012
DSAR: DSA aware routing with simultaneous DSA guiding pattern and double patterning assignment
J Ou, B Yu, X Xu, J Mitra, Y Lin, DZ Pan
Proceedings of the 2017 ACM on International Symposium on Physical Design, 91-98, 2017
DTCO for DSA-MP hybrid lithography with double-BCP materials in sub-7nm node
J Ou, X Xu, B Cline, G Yeric, DZ Pan
2017 IEEE International Conference on Computer Design (ICCD), 403-410, 2017
Graph-based redundant via insertion and guiding template assignment for DSA-MP
X Li, B Yu, J Ou, J Chen, DZ Pan, W Zhu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (11 …, 2018
Efficient DSA-DP hybrid lithography conflict detection and guiding template assignment
J Ou, B Cline, G Yeric, DZ Pan
Design-Process-Technology Co-optimization for Manufacturability XI 10148, 86-94, 2017
Redundant local-loop insertion for unidirectional routing
X Xu, Y Lin, M Li, J Ou, B Cline, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
Performance investigation of SRAM cells based on gate-all-around (GAA) Si nanowire transistor for ultra-low voltage applications
J Ou, R Huang, Y Liu, R Wang, Y Wang
2012 IEEE 11th International Conference on Solid-State and Integrated …, 2012
Improving analog/RF performance of multi-gate devices through multi-dimensional design optimization with awareness of variations and parasitics
Y Liu, R Huang, R Wang, J Ou, Y Wang
2012 International Electron Devices Meeting, 14.5. 1-14.5. 4, 2012
Design for manufacturing with directed self-assembly lithography
J Ou
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