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Saeideh Nabipour
Saeideh Nabipour
PhD Student at University of Bremen, Germany
Verified email at uni-bremen.de
Title
Cited by
Cited by
Year
Multimodal price prediction
A Zehtab-Salmasi, AR Feizi-Derakhshi, N Nikzad-Khasmakhi, ...
Annals of Data Science 10 (3), 619-635, 2023
62023
Error Detection Mechanism based on BCH Decoder and Root Finding of Polynomial over Finite Fields
S Nabipour, J Javidan, G Zare Fatin
Journal of mathematics and computer science, 2014
62014
Reduced-Reference image quality assessment based on 2-D discrete FFT and Edge Similarity
M Khorrami, Z Azimzadeh, S Nabipour
2015 9th Iranian Conference on Machine Vision and Image Processing (MVIP), 24-28, 2015
52015
Area-Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF (2m)
S Nabipour, GZ Fatin, J Javidan
arXiv:2007.08284, 2020
32020
Arithmetic Operators over Finite Field GF () for Error Correction Codes Application
S Nabipour, M Gholizade
arXiv preprint arXiv:2310.12319, 2023
2*2023
Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes
S Nabipour, J Javidan
arXiv preprint arXiv:2307.08084, 2023
12023
A Survey on Error Detection Mechanism based on Embedded High-Speed BCH Encoder & Decoder for Multi-Level Cell (MLC) NAND Flash Memor
S Nabipour
Programmable Device Circuits and Systems 10 (2), 2016
12016
BCH Decoder Design to Improve Memory Reliability and Error Correcting in Flash Memories
S Nabipour, J Javidan, G Zare Fatin, M Nooshyar
university of Mohaghegh Ardabili, 2015
12015
Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices
S Nabipour, J Javidan, R Drechsler
Memories-Materials, Devices, Circuits and Systems, 100099, 2024
2024
High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF (2m)
S Nabipour, J Javidan
arXiv preprint arXiv:2306.13347, 2023
2023
Area-Delay-Efficeint FPGA Design of 32-bit Euclid's GCD based on Sum of Absolute Difference
S Nabipour, M Gholizade, N Nabipour
arXiv preprint arXiv:2107.02762, 2021
2021
An Efficient Digital Watermarking Algorithm Based on DCT and BCH Error Correcting Code
S Nabipour, J Javidan, M Khorrami, J Azimzadeh
Journal of CiiT, arXiv:2108.01612, 2016
2016
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Articles 1–12