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Byron Ho
Byron Ho
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A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate …
C Auth, A Aliyarukunju, M Asoro, D Bergstrom, V Bhagwat, J Birdsall, ...
2017 IEEE International Electron Devices Meeting (IEDM), 29.1. 1-29.1. 4, 2017
3282017
Effectiveness of stressors in aggressively scaled FinFETs
N Xu, B Ho, M Choi, V Moroz, TJK Liu
IEEE Transactions on Electron Devices 59 (6), 1592-1598, 2012
512012
Design optimization of multigate bulk MOSFETs
B Ho, X Sun, C Shin, TJK Liu
IEEE transactions on electron devices 60 (1), 28-33, 2012
402012
Semiconductor device having fin-end stress-inducing features
B Ho, ML Hattendorf, JL Luce, EL Mays, EJ Thompson
US Patent 10,964,800, 2021
322021
Carrier-mobility enhancement via strain engineering in future thin-body MOSFETs
N Xu, B Ho, F Andrieu, L Smith, BY Nguyen, O Weber, T Poiroux, ...
IEEE electron device letters 33 (3), 318-320, 2012
322012
Replacement gate structures for advanced integrated circuit structure fabrication
B Ho, S Jaloviar, ML Hattendorf, CP Auth
US Patent 10,121,875, 2018
252018
Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) fully depleted SOI MOSFETs
N Xu, F Andrieu, B Ho, BY Nguyen, O Weber, C Mazuré, O Faynot, ...
2012 Symposium on VLSI Technology (VLSIT), 113-114, 2012
232012
Planar GeOI TFET performance improvement with back biasing
P Matheu, B Ho, ZA Jacobson, TJK Liu
IEEE transactions on electron devices 59 (6), 1629-1635, 2012
172012
IEEE International Electron Devices Meeting IEDM
C Auth, A Aliyarukunju, M Asoro, D Bergstrom, V Bhagwat, J Birdsall, ...
San Francisco, CA, 2018
162018
Evolutionary MOSFET structure and channel design for nanoscale CMOS technology
B Ho
University of California, Berkeley, 2012
132012
First demonstration of quasi-planar segmented-channel MOSFET design for improved scalability
B Ho, X Sun, N Xu, T Sako, K Maekawa, M Tomoyasu, Y Akasaka, ...
IEEE transactions on electron devices 59 (8), 2273-2276, 2012
112012
Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication
T Ghani, B Ho, ML Hattendorf, CP Auth
US Patent 10,756,204, 2020
102020
Continuous gate and fin spacer for advanced integrated circuit structure fabrication
HM Meyer, T Ahmet, B Ho, S Joshi, ML Hattendorf, CP Auth
US Patent App. 15/859,323, 2019
102019
Gate line plug structures for advanced integrated circuit structure fabrication
B Ho, ML Hattendorf, CP Auth
US Patent 10,121,882, 2018
92018
pMOSFET Performance Enhancement With StrainedChannels
B Ho, N Xu, TJK Liu
IEEE transactions on Electron devices 59 (5), 1468-1474, 2012
82012
Fabrication ofpMOSFETs Using Corrugated Substrates for Improvedand Reduced Layout-Width Dependence
B Ho, N Xu, B Wood, V Tran, S Chopra, Y Kim, BY Nguyen, O Bonnin, ...
IEEE transactions on electron devices 60 (1), 153-158, 2012
62012
Study of high-performance Ge pMOSFET scaling accounting for direct source-to-drain tunneling
B Ho, N Xu, TJK Liu
IEEE transactions on electron devices 58 (9), 2895-2902, 2011
62011
Fin cut and fin trim isolation for advanced integrated circuit structure fabrication
T Ghani, B Ho, CW Ward, ML Hattendorf, CP Auth
US Patent 10,460,993, 2019
52019
Fin end plug structures for advanced integrated circuit structure fabrication
B Ho, C Huang, E Thompson, J Luce, ML Hattendorf, CP Auth, EL Mays
US Patent 10,734,379, 2020
42020
Gate cut and fin trim isolation for advanced integrated circuit structure fabrication
T Ghani, B Ho, ML Hattendorf, CP Auth
US Patent 10,615,265, 2020
42020
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