| A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate … C Auth, A Aliyarukunju, M Asoro, D Bergstrom, V Bhagwat, J Birdsall, ... 2017 IEEE International Electron Devices Meeting (IEDM), 29.1. 1-29.1. 4, 2017 | 414 | 2017 |
| Semiconductor device having fin-end stress-inducing features B Ho, ML Hattendorf, JL Luce, EL Mays, EJ Thompson US Patent 10,964,800, 2021 | 51 | 2021 |
| Effectiveness of stressors in aggressively scaled FinFETs N Xu, B Ho, M Choi, V Moroz, TJK Liu IEEE Transactions on Electron Devices 59 (6), 1592-1598, 2012 | 51 | 2012 |
| Design optimization of multigate bulk MOSFETs B Ho, X Sun, C Shin, TJK Liu IEEE transactions on electron devices 60 (1), 28-33, 2012 | 45 | 2012 |
| Replacement gate structures for advanced integrated circuit structure fabrication B Ho, S Jaloviar, ML Hattendorf, CP Auth US Patent 10,121,875, 2018 | 41 | 2018 |
| Carrier-mobility enhancement via strain engineering in future thin-body MOSFETs N Xu, B Ho, F Andrieu, L Smith, BY Nguyen, O Weber, T Poiroux, ... IEEE electron device letters 33 (3), 318-320, 2012 | 35 | 2012 |
| Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication T Ghani, B Ho, ML Hattendorf, CP Auth US Patent 10,756,204, 2020 | 25 | 2020 |
| Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) fully depleted SOI MOSFETs N Xu, F Andrieu, B Ho, BY Nguyen, O Weber, C Mazuré, O Faynot, ... 2012 Symposium on VLSI Technology (VLSIT), 113-114, 2012 | 24 | 2012 |
| Planar GeOI TFET performance improvement with back biasing P Matheu, B Ho, ZA Jacobson, TJK Liu IEEE transactions on electron devices 59 (6), 1629-1635, 2012 | 21 | 2012 |
| Gate line plug structures for advanced integrated circuit structure fabrication B Ho, ML Hattendorf, CP Auth US Patent 10,121,882, 2018 | 17 | 2018 |
| Evolutionary MOSFET structure and channel design for nanoscale CMOS technology B Ho University of California, Berkeley, 2012 | 14 | 2012 |
| First demonstration of quasi-planar segmented-channel MOSFET design for improved scalability B Ho, X Sun, N Xu, T Sako, K Maekawa, M Tomoyasu, Y Akasaka, ... IEEE transactions on electron devices 59 (8), 2273-2276, 2012 | 11 | 2012 |
| pMOSFET Performance Enhancement With StrainedChannels B Ho, N Xu, TJK Liu IEEE transactions on Electron devices 59 (5), 1468-1474, 2012 | 9 | 2012 |
| Gate cut and fin trim isolation for advanced integrated circuit structure fabrication T Ghani, B Ho, ML Hattendorf, CP Auth US Patent 11,322,601, 2022 | 7 | 2022 |
| Replacement gate structures for advanced integrated circuit structure fabrication B Ho, S Jaloviar, ML Hattendorf, CP Auth US Patent 10,790,378, 2020 | 7 | 2020 |
| Gate cut and fin trim isolation for advanced integrated circuit structure fabrication T Ghani, B Ho, ML Hattendorf, CP Auth US Patent 10,304,940, 2019 | 7 | 2019 |
| Study of high-performance Ge pMOSFET scaling accounting for direct source-to-drain tunneling B Ho, N Xu, TJK Liu IEEE transactions on electron devices 58 (9), 2895-2902, 2011 | 7 | 2011 |
| Fin end plug structures for advanced integrated circuit structure fabrication B Ho, C Huang, E Thompson, J Luce, ML Hattendorf, CP Auth, EL Mays US Patent 10,734,379, 2020 | 6 | 2020 |
| Fabrication ofpMOSFETs Using Corrugated Substrates for Improvedand Reduced Layout-Width Dependence B Ho, N Xu, B Wood, V Tran, S Chopra, Y Kim, BY Nguyen, O Bonnin, ... IEEE transactions on electron devices 60 (1), 153-158, 2012 | 6 | 2012 |
| Gate cut and fin trim isolation for advanced integrated circuit structure fabrication T Ghani, B Ho, ML Hattendorf, CP Auth US Patent 10,615,265, 2020 | 5 | 2020 |
