| High performance and low power transistors integrated in 65nm bulk CMOS technology Z Luo, A Steegen, M Eller, R Mann, C Baiocco, P Nguyen, L Kim, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 105 | 2004 |
| A 0.13/spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications T Schiml, S Biesemans, G Brase, L Burrell, A Cowley, KC Chen, ... 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2001 | 84 | 2001 |
| 65nm CMOS technology for low power applications A Steegen, R Mo, R Mann, MC Sun, M Eller, G Leake, D Vietzke, A Tilke, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 64-67, 2005 | 61 | 2005 |
| High performance 50 nm CMOS devices for microprocessor and embedded processor core applications SF Huang, CY Lin, YS Huang, T Schafbauer, M Eller, YC Cheng, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 54 | 2001 |
| Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond C Davis, JH Ku, T Schiml, J Sudijono, I Yang, A Steegen, D Coolbough, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 60-61, 2006 | 42 | 2006 |
| A modular 0.13/spl mu/m bulk CMOS technology for high performance and low power applications LK Han, S Biesemans, J Heidenreich, K Houlihan, C Lin, V McGahay, ... 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2000 | 37 | 2000 |
| 'System on a chip'technology platform for 0.18/spl mu/m digital, mixed signal and eDRAM applications R Mahnkopf, KH Allers, M Armacost, A Augustin, J Barth, G Brase, ... International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 32 | 1999 |
| Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology T Schafbauer, J Brighten, YC Chen, L Clevenger, M Commons, A Cowley, ... 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2002 | 26 | 2002 |
| Hot carrier reliability for 0.13/spl mu/m CMOS technology with dual gate oxide thickness C Lin, S Biesemans, LK Han, K Houlihan, T Schiml, K Schruefer, C Wann, ... International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000 | 25 | 2000 |
| IEDM Tech. Dig. A Steegen, M Stucchi, A Lauwers, K Maex IEDM Tech. Dig 497, 1999 | 12 | 1999 |
| A 45nm low cost low power platform by using integrated dual-stress-liner technology J Yuan, S Tan, Y Lee, J Kim, R Lindsay, V Sardesai, T Hook, R Amos, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 100-101, 2006 | 11 | 2006 |
| A 0.18 um Dual Gate (3.5 nm/6.8 nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications B Agarwala, M Armacost, S Biesemans, L Burrell, B Chen, K Han, ... 29th European Solid-State Device Research Conference, 1999 | 6 | 1999 |
| Semiconductor devices T Schiml, M Eller US Patent 8,242,550, 2012 | 5 | 2012 |
| W-polycide dual-gate structure for sub-1/4 micron low-voltage CMOS technology J Bevk, GE Georgiou, M Frei, PJ Silverman, EJ Lloyd, Y Kim, H Luftman, ... Proceedings of International Electron Devices Meeting, 893-896, 1995 | 4 | 1995 |
| RTA processing of W-polycide dual-gate sub-micron structures for low-voltage CMOS technology J Bevk, M Furtsch, GE Georgiou, SJ Hillenius, D Schielein, T Schiml, ... MRS Online Proceedings Library (OPL) 429, 115, 1996 | 1 | 1996 |
| Semiconductor devices and methods of manufacture thereof T Schiml, M Eller US Patent 7,776,726, 2010 | | 2010 |
| Mechanism of Threshold Voltage Shift (ΔV_< th>) Caused by Negative Bias Temperature Instability (NBTI) in Deep Sub-Micron pMOSFETs LIN Chih-Yung, J CHEN, K SCHRUEFER, T SCHIML, Z YANG, ... Extended abstracts of the... Conference on Solid State Devices and Materials …, 2001 | | 2001 |
| Measurement of Dopant Lateral Diffusion in Layered Thin Films J Bevk, M Furtsch, T Schiml, GE Georgiou, HS Luftman APS March Meeting Abstracts, F20. 11, 1997 | | 1997 |
| Measurement of lateral dopant diffusion in rapid thermal annealed W-polycide gate structures T Schiml, J Bevk, M Furtsch, GE Georgiou, R Cirelli, WM Mansfield, ... MRS Online Proceedings Library (OPL) 429, 121, 1996 | | 1996 |
| High Performance and Low Power Transistors Integrated in 65nm Bulk CMOS Technology T Schiml, J Sudijono, I Yang, C Wann dimension 3, 61, 0 | | |
