Pengju Ren
Pengju Ren
在 的电子邮件经过验证
Hybrid-augmented intelligence: collaboration and cognition
N Zheng, Z Liu, P Ren, Y Ma, S Chen, S Yu, J Xue, B Chen, F Wang
Frontiers of Information Technology & Electronic Engineering 18 (2), 153-179, 2017
Scalable, accurate multicore simulation in the 1000-core era
M Lis, P Ren, MH Cho, KS Shim, CW Fletcher, O Khan, S Devadas
(IEEE ISPASS) IEEE International Symposium on Performance Analysis of …, 2011
Hornet: A cycle-level multicore simulator
P Ren, M Lis, MH Cho, KS Shim, CW Fletcher, O Khan, N Zheng, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
DARSIM: a parallel cycle-level NoC simulator
M Lis, KS Shim, MH Cho, P Ren, O Khan, S Devadas
MoBS 2010-Sixth Annual Workshop on Modeling, Benchmarking and Simulation, 2010
Centripetalnet: Pursuing high-quality keypoint pairs for object detection
Z Dong, G Li, Y Liao, F Wang, P Ren, C Qian
Proceedings of the IEEE/CVF conference on computer vision and pattern …, 2020
Fault-tolerant routing for on-chip network without using virtual channels
P Ren, Q Meng, X Ren, N Zheng
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
Parallel scaling engine for multi-view 3DTV display and method thereof
P Ren, WU Xiaogang, H Bi, H Wang, H Sun, B Chen, N Zheng
US Patent 9,924,153, 2018
Design space exploration of neural network activation function circuits
T Yang, Y Wei, Z Tu, H Zeng, MA Kinsy, N Zheng, P Ren
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
Maximum total correntropy diffusion adaptation over networks with noisy links
Y He, F Wang, S Wang, P Ren, B Chen
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2), 307-311, 2018
Fault-aware load-balancing routing for 2D-mesh and torus on-chip network topologies
P Ren, MA Kinsy, N Zheng
IEEE Transactions on Computers 65 (3), 873-887, 2015
A deadlock-free and connectivity-guaranteed methodology for achieving fault-tolerance in on-chip networks
P Ren, X Ren, S Sane, MA Kinsy, N Zheng
IEEE transactions on computers 65 (2), 353-366, 2015
A high-throughput fixed-point complex divider for FPGAs
D Wang, P Ren, L Liu
IEICE Electronics Express 10 (4), 20120879-20120879, 2013
An efficient motion adaptive de-interlacing and its VLSI architecture design
H Sun, N Zheng, C Ge, D Wang, P Ren
2008 IEEE Computer Society Annual Symposium on VLSI, 455-458, 2008
Hardware implementation of KLMS algorithm using FPGA
X Ren, P Ren, B Chen, T Min, N Zheng
2014 International Joint Conference on Neural Networks (IJCNN), 2276-2281, 2014
Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology
H Sun, P Ren, N Zheng, T Zhang, T Li
Microprocessors and Microsystems 35 (4), 371-381, 2011
Toward an efficient multiview display processing architecture for 3DTV
P Ren, X Zhang, H Bi, H Sun, N Zheng
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (6), 705-709, 2016
Robust power system state estimation with minimum error entropy unscented Kalman filter
L Dang, B Chen, S Wang, W Ma, P Ren
IEEE Transactions on Instrumentation and Measurement 69 (11), 8797-8808, 2020
Linear and nonlinear regression-based maximum correntropy extended Kalman filtering
X Liu, Z Ren, H Lyu, Z Jiang, P Ren, B Chen
IEEE transactions on systems, man, and cybernetics: Systems, 2019
Asymmetric correntropy for robust adaptive filtering
B Chen, Z Li, Y Li, P Ren
arXiv preprint arXiv:1911.11855, 2019
Neuromorphic implementation of a recurrent neural network for EMG classification
Y Ma, E Donati, B Chen, P Ren, N Zheng, G Indiveri
2020 2nd IEEE International Conference on Artificial Intelligence Circuits …, 2020
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