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Michihiro Koibuchi
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A case for random shortcut topologies for HPC interconnects
M Koibuchi, H Matsutani, H Amano, DF Hsu, H Casanova
ACM Sigarch Computer Architecture News 40 (3), 177-188, 2012
1862012
A lightweight fault-tolerant mechanism for network-on-chip
M Koibuchi, H Matsutani, H Amano, T Mark Pinkston
Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium …, 2008
1802008
Prediction router: Yet another low latency on-chip router architecture
H Matsutani, M Koibuchi, H Amano, T Yoshinaga
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
1352009
Run-time power gating of on-chip routers using look-ahead routing
H Matsutani, M Koibuchi, H Amano, D Wang
2008 Asia and South Pacific Design Automation Conference, 55-60, 2008
1312008
A Survey and Evaluation of Topology Agnostic Deterministic Routing Algorithms
J Flich, T Skeie, A Mejía, O Lysne, P López, A Robles, J Duato, ...
Parallel and Distributed Systems, IEEE Transactions on, 1-1, 2011
1302011
Ultra fine-grained run-time power gating of on-chip routers for cmps
H Matsutani, M Koibuchi, D Ikebuchi, K Usami, H Nakamura, H Amano
Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on, 61-68, 2010
122*2010
PopCache: Cache more or less based on content popularity for information-centric networking
K Suksomboon, S Tarnoi, Y Ji, M Koibuchi, K Fukuda, S Abe, N Motonori, ...
38th Annual IEEE conference on local computer networks, 236-243, 2013
1102013
L-turn routing: An adaptive routing in irregular networks
M Koibuchi, A Funahashi, A Jouraku, H Amano
International Conference on Parallel Processing, 2001., 383-392, 2001
1022001
Tightly-coupled multi-layer topologies for 3-D NOCs
H Matsutani, M Koibuchi, H Amano
Parallel Processing, 2007. ICPP 2007. International Conference on, 75-75, 2007
1002007
Networks-on-chips: Theory and Practice
F Gebali, H Elmiligi, MW El-Kharashi
CRC Press, Inc., 2009
952009
3D NoC with inductive-coupling links for building-block SiPs
Y Take, H Matsutani, D Sasaki, M Koibuchi, T Kuroda, H Amano
IEEE Transactions on Computers 63 (3), 748-763, 2012
782012
Adding slow-silent virtual channels for low-power on-chip networks
H Matsutani, M Koibuchi, D Wang, H Amano
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 23-32, 2008
752008
AxNoC: Low-power approximate network-on-chips using critical-path isolation
AB Ahmed, D Fujiki, H Matsutani, M Koibuchi, H Amano
2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2018
642018
Low-latency wireless 3D NoCs via randomized shortcut chips
H Matsutani, M Koibuchi, I Fujiwara, T Kagami, Y Take, T Kuroda, ...
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
592014
A case for wireless 3D NoCs for CMPs
H Matsutani, P Bogdan, R Marculescu, Y Take, D Sasaki, H Zhang, ...
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 23-28, 2013
592013
Layout-conscious random topologies for HPC off-chip interconnects
M Koibuchi, I Fujiwara, H Matsutani, H Casanova
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
532013
Performance, cost, and energy evaluation of fat h-tree: A cost-efficient tree-based on-chip network
H Matsutani, M Koibuchi, H Amano
Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE …, 2007
512007
Descending layers routing: A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies
M Koibuchi, A Jouraku, K Watanabe, H Amano
2003 International Conference on Parallel Processing, 2003. Proceedings …, 2003
502003
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs
H Matsutani, M Koibuchi, D Ikebuchi, K Usami, H Nakamura, H Amano
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2011
452011
Semantic router using data stream to enrich services
K Inoue
Proceedings of the CFI, June 2008, 20-23, 2008
442008
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