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Dmitry Yakimets
Dmitry Yakimets
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Cited by
Year
Device exploration of nanosheet transistors for sub-7-nm technology node
D Jang, D Yakimets, G Eneman, P Schuddinck, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 64 (6), 2707-2713, 2017
2462017
Vertical GAAFETs for the ultimate CMOS scaling
D Yakimets, G Eneman, P Schuddinck, TH Bao, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 62 (5), 1433-1439, 2015
2072015
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ...
IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018
1282018
Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration
H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ...
2017 IEEE international electron devices meeting (IEDM), 37.4. 1-37.4. 4, 2017
1252017
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
1052017
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ...
2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019
1032019
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ...
2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016
772016
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
S Sakhare, M Perumkunnil, TH Bao, S Rao, W Kim, D Crotti, F Yasin, ...
2018 IEEE International Electron Devices Meeting (IEDM), 18.3. 1-18.3. 4, 2018
712018
Vertical nanowire FET integration and device aspects
A Veloso, E Altamirano-Sánchez, S Brus, BT Chan, M Cupak, M Dehan, ...
ECS Transactions 72 (4), 31, 2016
562016
Vertical device architecture for 5nm and beyond: device & circuit implications
AVY Thean, D Yakimets, TH Bao, P Schuddinck, S Sakhare, MG Bardon, ...
2015 Symposium on VLSI Technology (VLSI Technology), T26-T27, 2015
562015
The impact of sequential-3D integration on semiconductor scaling roadmap
A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017
552017
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
P Weckx, J Ryckaert, V Putcha, A De Keersgieter, J Boemmels, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2017
502017
Holisitic device exploration for 7nm node
P Raghavan, MG Bardon, D Jang, P Schuddinck, D Yakimets, J Ryckaert, ...
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-5, 2015
482015
Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node
C Pan, P Raghavan, D Yakimets, P Debacker, F Catthoor, N Collaert, ...
IEEE Transactions on Electron Devices 62 (10), 3125-3132, 2015
482015
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
TH Bao, D Yakimets, J Ryckaert, I Ciofi, R Baert, A Veloso, J Boemmels, ...
2014 44th European Solid State Device Research Conference (ESSDERC), 102-105, 2014
472014
Device-, circuit-& block-level evaluation of CFET in a 4 track library
P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ...
2019 Symposium on VLSI Technology, T204-T205, 2019
462019
Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells
MG Bardon, Y Sherazi, D Jang, D Yakimets, P Schuddinck, R Baert, ...
2018 IEEE Symposium on VLSI Technology, 143-144, 2018
442018
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
MG Bardon, P Schuddinck, P Raghavan, D Jang, D Yakimets, A Mercha, ...
2015 International Conference on IC Design & Technology (ICICDT), 1-4, 2015
442015
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
MG Bardon, V Moroz, G Eneman, P Schuddinck, M Dehan, D Yakimets, ...
2013 Symposium on VLSI Technology, T114-T115, 2013
412013
Junctionless versus inversion-mode lateral semiconductor nanowire transistors
A Veloso, P Matagne, E Simoen, B Kaczer, G Eneman, H Mertens, ...
Journal of Physics: Condensed Matter 30 (38), 384002, 2018
372018
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