Chaotic weights: A novel approach to protect intellectual property of deep neural networks N Lin, X Chen, H Lu, X Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 50 | 2020 |
Tetris: Re-architecting convolutional neural network computation for machine learning accelerators H Lu, X Wei, N Lin, G Yan, X Li 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 34 | 2018 |
Poseidon: Practical homomorphic encryption accelerator Y Yang, H Zhang, S Fan, H Lu, M Zhang, X Li 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 22 | 2023 |
Distilling bit-level sparsity parallelism for general purpose deep learning acceleration H Lu, L Chang, C Li, Z Zhu, S Lu, Y Liu, M Zhang MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 21 | 2021 |
RISO: Relaxed network-on-chip isolation for cloud processors H Lu, G Yan, Y Han, B Fu, X Li Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 14 | 2013 |
ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation H Lu, G Yan, Y Han, Y Wang, X Li The 20th Asia and South Pacific Design Automation Conference, 142-147, 2015 | 12 | 2015 |
Streamline ring oram accesses through spatial and temporal optimization D Cao, M Zhang, H Lu, X Ye, D Fan, Y Che, R Wang 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 11 | 2021 |
When deep learning meets the edge: Auto-masking deep neural networks for efficient machine learning on edge devices N Lin, H Lu, X Hu, J Gao, M Zhang, X Li 2019 IEEE 37th International Conference on Computer Design (ICCD), 506-514, 2019 | 7 | 2019 |
BitX: Empower versatile inference with hardware runtime pruning H Li, H Lu, J Huang, W Wang, M Zhang, W Chen, L Chang, X Li Proceedings of the 50th International Conference on Parallel Processing, 1-12, 2021 | 6 | 2021 |
VNet: a versatile network for efficient real-time semantic segmentation N Lin, H Lu, J Gao, S Qiao, X Li 2019 IEEE 37th International Conference on Computer Design (ICCD), 626-629, 2019 | 4 | 2019 |
Architecting effectual computation for machine learning accelerators H Lu, M Zhang, Y Han, Q Wang, H Li, X Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 4 | 2019 |
ShuttleNoC: Power-adaptable communication infrastructure for many-core processors H Lu, Y Chang, G Yan, N Lin, X Wei, X Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 4 | 2018 |
RISO: Enforce noninterfered performance with relaxed network-on-chip isolation in many-core cloud processors H Lu, B Fu, Y Wang, Y Han, G Yan, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015 | 3 | 2015 |
VNet: a versatile network to train real-time semantic segmentation models on a single GPU W Li, N Lin, M Zhang, H Lu, X Chen, X Li Science China. Information Sciences 65 (3), 139105, 2022 | 2 | 2022 |
HeadStart: Enforcing optimal inceptions in pruning deep neural networks for efficient inference on GPGPUS N Lin, H Lu, X Wei, X Li Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 2 | 2019 |
BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks H Li, H Lu, H Wang, S Deng, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (1), 90-103, 2022 | 1 | 2022 |
PowerTrader: Enforcing autonomous power management for future large-scale many-core processors H Lu, G Yan, Y Han, X Li IEEE Transactions on Multi-Scale Computing Systems 3 (4), 283-295, 2017 | 1 | 2017 |
Mortar: Morphing the Bit Level Sparsity for General Purpose Deep Learning Acceleration Y Gao, H Li, K Zhang, X Yu, H Lu Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | | 2023 |
Redeeming chip-level power efficiency by collaborative management of the computation and communication N Lin, H Lu, X Wei, X Li Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | | 2019 |