| MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes M Jang, KS Yun Micro and Nano Systems Letters 5, 1-5, 2017 | 27 | 2017 |
| Improving memory reliability by bounding DRAM faults: DDR5 improved reliability features K Criss, K Bains, R Agarwal, T Bennett, T Grunzke, JK Kim, H Chung, ... Proceedings of the International Symposium on Memory Systems, 317-322, 2020 | 20 | 2020 |
| 23.3 A 4.8 Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications N Kwak, SH Kim, KH Lee, CK Baek, MS Jang, Y Joo, SH Lee, WY Lee, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 392-393, 2017 | 19 | 2017 |
| HBM3 RAS: Enhancing resilience at scale S Gurumurthi, K Lee, M Jang, V Sridharan, A Nygren, Y Ryu, K Sohn, ... IEEE Computer Architecture Letters 20 (2), 158-161, 2021 | 17 | 2021 |
| Piezoelectric energy harvester operated by noncontact mechanical frequency up-conversion using shell cantilever structure M Jang, S Song, YH Park, KS Yun Japanese Journal of Applied Physics 54 (6S1), 06FP08, 2015 | 14 | 2015 |
| HBM3: Enabling Memory Resilience at Scale S Gurumurthi, K Lee, M Jang, V Sridharan, A Nygren, Y Ryu, K Sohn, ... CAL, 2021 | 4 | 2021 |
| Memory and operation method of memory J Munseon, H Chung US Patent 11,462,286, 2022 | 3 | 2022 |
| Memory system and operating method thereof MS Jang, H Chung, TK Kim US Patent 11,265,022, 2022 | 2 | 2022 |
| Semiconductor device MS Jang, SH Kim, BY Kim US Patent App. 15/170,383, 2017 | 2 | 2017 |
| Power driving device and semiconductor device including the same MS Jang US Patent App. 14/810,925, 2016 | 1 | 2016 |
| Amplification circuit of semiconductor apparatus MS Jang US Patent 9,154,092, 2015 | 1 | 2015 |
| Memory device including error correction device JH Jeong, DS Kim, SW Yoon, AR RIM, MS Jang US Patent App. 18/314,147, 2024 | | 2024 |
| Memory including error correction circuit and operating method thereof JH Jeong, DS Kim, J Munseon US Patent App. 18/170,530, 2024 | | 2024 |
| Error processing circuit, memory and operation method of the memory JH Jeong, H Chung, DS Kim, J Munseon US Patent App. 18/169,880, 2024 | | 2024 |
| Memory device including error correction device JH Jeong, DS Kim, MS Jang US Patent App. 18/080,282, 2024 | | 2024 |
| Memory and operation method of memory J Munseon, HJ Chung, JR Kim US Patent 11,928,026, 2024 | | 2024 |
| Memory, memory system and operation method of memory system J Munseon, H Chung, JR Kim US Patent App. 18/482,016, 2024 | | 2024 |
| Memory and operation method of memory JH Jeong, DS Kim, J Munseon US Patent App. 18/357,336, 2023 | | 2023 |
| Memory, memory system and operation method of memory system J Munseon, H Chung, JR Kim US Patent 11,817,169, 2023 | | 2023 |
| Memory, operation method of memory, and operation method of memory system J Munseon, H Chung US Patent App. 17/883,096, 2023 | | 2023 |
