Angada Sachid
Angada Sachid
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MoS2 transistors with 1-nanometer gate lengths
SB Desai, SR Madhvapathy, AB Sachid, JP Llinas, Q Wang, GH Ahn, ...
Science 354 (6308), 99-102, 2016
Field-effect transistors built from all two-dimensional material components
T Roy, M Tosun, JS Kang, AB Sachid, SB Desai, M Hettick, CC Hu, ...
ACS nano 8 (6), 6259-6264, 2014
High-Gain Inverters Based on WSe2 Complementary Field-Effect Transistors
M Tosun, S Chuang, H Fang, AB Sachid, M Hettick, Y Lin, Y Zeng, ...
ACS nano 8 (5), 4948-4953, 2014
Negative capacitance in short-channel FinFETs externally connected to an epitaxial ferroelectric capacitor
AI Khan, K Chatterjee, JP Duarte, Z Lu, A Sachid, S Khandelwal, ...
IEEE Electron Device Letters 37 (1), 111-114, 2015
Improved subthreshold swing and short channel effect in FDSOI n-channel negative capacitance field effect transistors
D Kwon, K Chatterjee, AJ Tan, AK Yadav, H Zhou, AB Sachid, R Dos Reis, ...
IEEE Electron Device Letters 39 (2), 300-303, 2017
Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization
AB Sachid, CR Manoj, DK Sharma, VR Rao
IEEE Electron Device Letters 29 (1), 128-130, 2007
Monolithic 3D CMOS using layered semiconductors
AB Sachid, M Tosun, SB Desai, CY Hsu, DH Lien, SR Madhvapathy, ...
Advanced Materials 28 (13), 2547-2554, 2016
Insights into the design and optimization of tunnel-FET devices and circuits
A Pal, AB Sachid, H Gossner, VR Rao
IEEE Transactions on Electron devices 58 (4), 1045-1053, 2011
BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control
S Khandelwal, YS Chauhan, DD Lu, S Venugopalan, MAU Karim, ...
IEEE Transactions on Electron Devices 59 (8), 2019-2026, 2012
Compact models of negative-capacitance FinFETs: Lumped and distributed charge models
JP Duarte, S Khandelwal, AI Khan, A Sachid, YK Lin, HL Chang, ...
2016 IEEE International Electron Devices Meeting (IEDM), 30.5. 1-30.5. 4, 2016
Air stable n-doping of WSe2 by silicon nitride thin films with tunable fixed charge density
K Chen, D Kiriya, M Hettick, M Tosun, TJ Ha, SR Madhvapathy, S Desai, ...
Apl Materials 2 (9), 092504, 2014
Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?
AB Sachid, R Francis, MS Baghini, DK Sharma, KH Bach, R Mahnkopf, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Engineering negative differential resistance in NCFETs for analog applications
H Agarwal, P Kushwaha, JP Duarte, YK Lin, AB Sachid, MY Kao, ...
IEEE Transactions on Electron Devices 65 (5), 2033-2039, 2018
Semiconductor devices
H Gossner, R Rao, A Sachid, A Pal, R Asra
US Patent 8,405,121, 2013
FinFET with High-κ Spacers for Improved Drive Current
AB Sachid, MC Chen, C Hu
IEEE Electron Device Letters 37 (7), 835 - 838, 2016
Denser and more stable SRAM using FinFETs with multiple fin heights
AB Sachid, C Hu
IEEE Transactions on Electron Devices 59 (8), 2037-2041, 2012
FinFET with encased air-gap spacers for high-performance and low-energy circuits
AB Sachid, YM Huang, YJ Chen, CC Chen, DD Lu, MC Chen, C Hu
IEEE Electron Device Letters 38 (1), 16-19, 2016
Circuit performance analysis of negative capacitance FinFETs
S Khandelwal, AI Khan, JP Duarte, AB Sachid, S Salahuddin, C Hu
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Negative capacitance, n-channel, Si FinFETs: Bi-directional sub-60 mV/dec, negative DIBL, negative differential resistance and improved short channel effect
H Zhou, D Kwon, AB Sachid, Y Liao, K Chatterjee, AJ Tan, AK Yadav, ...
2018 IEEE Symposium on VLSI Technology, 53-54, 2018
Extraction of isothermal condition and thermal network in UTBB SOI MOSFETs
MA Karim, YS Chauhan, S Venugopalan, AB Sachid, DD Lu, BY Nguyen, ...
IEEE Electron Device Letters 33 (9), 1306-1308, 2012
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