| Ultralow-power design in near-threshold region D Markovic, CC Wang, LP Alarcon, TT Liu, JM Rabaey Proceedings of the IEEE 98 (2), 237-252, 2010 | 523 | 2010 |
| Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications M Spencer, F Chen, CC Wang, R Nathanael, H Fariborzi, A Gupta, H Kam, ... IEEE Journal of Solid-State Circuits 46 (1), 308-320, 2010 | 221 | 2010 |
| Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications F Chen, M Spencer, R Nathanael, C Wang, H Fariborzi, A Gupta, H Kam, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 150-151, 2010 | 87 | 2010 |
| Analysis and demonstration of MEM-relay power gating H Fariborzi, M Spencer, V Karkare, J Jeon, R Nathanael, C Wang, F Chen, ... IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 55 | 2010 |
| A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing FL Yuan, CC Wang, TH Yu, D Marković IEEE Journal of Solid-State Circuits 50 (1), 137-149, 2014 | 53 | 2014 |
| Delay estimation and sizing of CMOS logic using logical effort with slope correction CC Wang, D Markovic IEEE Transactions on Circuits and Systems II: Express Briefs 56 (8), 634-638, 2009 | 28 | 2009 |
| Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same CC Wang US Patent 9,793,898, 2017 | 17 | 2017 |
| An automated fixed-point optimization tool in MATLAB XSG/SynDSP environment CC Wang, C Shi, RW Brodersen, D Marković International Scholarly Research Notices 2011, 2011 | 17 | 2011 |
| Multiplier-accumulator circuit, logic tile architecture for multiply-accumulate, and IC including logic tile array CC Wang US Patent 10,693,469, 2020 | 11 | 2020 |
| Network Architectures for Boundary-Less Hierarchical Interconnects C Wang, D Markovic US Patent App. 14/777,477, 2016 | 11 | 2016 |
| Multiplier-Accumulator Circuitry and Pipeline using Floating Point Data, and Methods of using Same FA Ware, CC Wang, FL Yuan, NU Natu US Patent App. 16/900,319, 2020 | 10 | 2020 |
| A 1.1 GOPS/mW FPGA chip with hierarchical interconnect fabric CC Wang, FL Yuan, H Chen, D Markovic 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 136-137, 2011 | 10 | 2011 |
| Block memory layout and architecture for programmable logic IC, and method of operating same GR Tate, CC Wang US Patent 9,973,194, 2018 | 9 | 2018 |
| Multiplexer-memory cell circuit, layout thereof and method of manufacturing same CC Wang US Patent 9,543,958, 2017 | 9 | 2017 |
| Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof CC Wang US Patent 9,240,791, 2016 | 9 | 2016 |
| Test circuitry and techniques for logic tiles of FPGA CC Wang US Patent 10,523,209, 2019 | 7 | 2019 |
| Fine-grained power gating in FPGA interconnects C Wang, D Markovic US Patent 9,923,555, 2018 | 6 | 2018 |
| Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network CC Wang US Patent 9,906,225, 2018 | 6 | 2018 |
| Multiplexer-memory cell circuit, layout thereof and method of manufacturing same CC Wang US Patent 9,755,651, 2017 | 6 | 2017 |
| Clock architecture, including clock mesh fabric, for FPGA, and method of operating same NU Natu, AM Abhyankar, CC Wang US Patent 10,348,308, 2019 | 5 | 2019 |
