| Vertical P-TFET with a P-type SiGe pocket W Li, JCS Woo IEEE Transactions on Electron Devices 67 (4), 1480-1484, 2020 | 60 | 2020 |
| Optimization and scaling of Ge-pocket TFET W Li, JCS Woo IEEE Transactions on Electron Devices 65 (12), 5289-5294, 2018 | 41 | 2018 |
| Source/drain extension doping engineering for variability suppression and performance enhancement in 3-nm node FinFETs P Lu, B Colombeau, S Hung, W Li, X Duan, Y Li, EM Bazizi, S Natarajan, ... IEEE Transactions on Electron Devices 68 (3), 1352-1357, 2021 | 13 | 2021 |
| Parasitic resistance modeling and optimization for 10nm-node FinFET X Duan, P Lu, W Li, JCS Woo 2018 18th International Workshop on Junction Technology (IWJT), 1-4, 2018 | 5 | 2018 |
| Corrections to “Optimization and Scaling of Ge-Pocket TFET”[Dec 18 5289-5294] W Li IEEE Transactions on Electron Devices 67 (3), 1361-1361, 2020 | | 2020 |
| SiGe-Pocket Tunnel FETs for Low Power Logic Applications W Li University of California, Los Angeles, 2019 | | 2019 |
| Advanced Technology for Ultra-Low Power System-on-Chip (SoC) J Woo, W Li, P Lu, ... | | 2017 |
