| OpenASIP 2.0: co-design toolset for RISC-V application-specific instruction-set processors K Hepola, J Multanen, P Jääskeläinen 2022 IEEE 33rd International Conference on Application-specific Systems …, 2022 | 7 | 2022 |
| Programmable dictionary code compression for instruction stream energy efficiency J Multanen, K Hepola, P Jääskeläinen 2020 IEEE 38th International Conference on Computer Design (ICCD), 356-363, 2020 | 4 | 2020 |
| Energy-efficient instruction delivery in embedded systems with domain wall memory J Multanen, K Hepola, AA Khan, J Castrillon, P Jääskeläinen IEEE Transactions on Computers 71 (9), 2010-2021, 2021 | 2 | 2021 |
| Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode K Hepola, J Multanen, P Jääskeläinen IEEE Transactions on Computers, 2023 | 1 | 2023 |
| AEx: Automated high-level synthesis of compiler programmable co-processors A Hirvonen, T Leppänen, K Hepola, J Multanen, J Hoozemans, ... Journal of Signal Processing Systems 95 (9), 1051-1065, 2023 | 1 | 2023 |
| Dual-IS: Instruction set modality for efficient instruction level parallelism K Hepola, J Multanen, P Jääskeläinen International Conference on Architecture of Computing Systems, 17-32, 2022 | 1 | 2022 |
| Generation of Customized RISC-V Implementations K Hepola | | 2022 |
| RISC-V-arkkitehtuurin avoimen lähdekoodin FPGA-toteutukset K Hepola | | 2020 |
