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Kari Hepola
Kari Hepola
Doctoral Researcher, Tampere University
Verified email at tuni.fi
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Cited by
Year
OpenASIP 2.0: co-design toolset for RISC-V application-specific instruction-set processors
K Hepola, J Multanen, P Jääskeläinen
2022 IEEE 33rd International Conference on Application-specific Systems íK, 2022
62022
Programmable dictionary code compression for instruction stream energy efficiency
J Multanen, K Hepola, P Jääskeläinen
2020 IEEE 38th International Conference on Computer Design (ICCD), 356-363, 2020
32020
Energy-efficient instruction delivery in embedded systems with domain wall memory
J Multanen, K Hepola, AA Khan, J Castrillon, P Jääskeläinen
IEEE Transactions on Computers 71 (9), 2010-2021, 2021
22021
Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode
K Hepola, J Multanen, P Jääskeläinen
IEEE Transactions on Computers, 2023
12023
AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors
A Hirvonen, T Leppänen, K Hepola, J Multanen, J Hoozemans, ...
Journal of Signal Processing Systems 95 (9), 1051-1065, 2023
12023
Dual-IS: Instruction set modality for efficient instruction level parallelism
K Hepola, J Multanen, P Jääskeläinen
International Conference on Architecture of Computing Systems, 17-32, 2022
12022
Generation of Customized RISC-V Implementations
K Hepola
2022
RISC-V-arkkitehtuurin avoimen lähdekoodin FPGA-toteutukset
K Hepola
2020
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