| Methods of forming semiconductor structures having stair step structures JB Matovu, DS Meyaard, G Damarla, SSS Vegunta, K Shrotri, S Saraf, ... US Patent 10,269,625, 2019 | 15 | 2019 |
| Electroplating: Applications in the Semiconductor Industry JK Jhothiraman, B Rajesh Advances in Chemical Engineering and Science 9 (2), 239-261, 2019 | 11 | 2019 |
| Semiconductor devices including a stair step structure, and related methods JB Matovu, DS Meyaard, G Damarla, SSS Vegunta, K Shrotri, S Saraf, ... US Patent 10,600,682, 2020 | 8 | 2020 |
| Microelectronic devices with polysilicon fill material between opposing staircase structures, and related devices, systems, and methods JK Jhothiraman, JM Meldrim, L Xu US Patent 11,088,088, 2021 | 5 | 2021 |
| Application of process simulation for comparison of contactless and conventional electrodeposition methods for 3D packaging M Zhao, K Jakes, K Luke, J Kishore, R Gouk, S Verhaverbeke, ... ECS Journal of Solid State Science and Technology 5 (9), P483, 2016 | 4 | 2016 |
| Contamination of ultra-high-purity (UHP) gas distribution systems by back diffusion of impurities R Dittler, J Kishore, C Geisert, F Shadman Journal of the IEST 57 (1), 63-76, 2014 | 4 | 2014 |
| Rinsing of High-Aspect-Ratio Features on Patterned Wafers CC Chiang, J Kishore, S Raghavan, F Shadman IEEE Transactions on Semiconductor Manufacturing 30 (1), 60-68, 2016 | 3 | 2016 |
| Pressure cycling for purging of dead spaces in high‐purity gas delivery systems J Kishore, F Shadman, R Dittler, G Carl AIChE Journal 61 (11), 3973-3980, 2015 | 3 | 2015 |
| Microelectronic devices including stair step structures, and related electronic devices and methods JK Jhothiraman, K Shrotri, MJ King US Patent 11,411,013, 2022 | 2 | 2022 |
| Integrated circuitry, memory arrays comprising strings of memory cells, methods used in forming integrated circuitry, and methods used in forming a memory array comprising … C Tiwari, JK Jhothiraman US Patent 11,302,712, 2022 | 2 | 2022 |
| Run-Away Energetic Reactions in the Exhaust of Deposition Reactors F Chang, Yen-Hsun, Kishore, Jivaan, Shadman Advances in Chemical Engineering and Science 9 (2), 223-238, 2019 | 2 | 2019 |
| Microelectronic devices with a polysilicon structure adjacent a staircase structure, and related methods JK Jhothiraman, JM Meldrim, L Xu US Patent 11,710,710, 2023 | 1 | 2023 |
| Stair step structures including insulative materials, and related devices JB Matovu, DS Meyaard, G Damarla, SSS Vegunta, K Shrotri, S Saraf, ... US Patent 11,088,017, 2021 | 1 | 2021 |
| Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems S Luo, L Xu, X Li, JK Jhothiraman, MA Baboli US Patent 11,978,705, 2024 | | 2024 |
| METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS M Baboli, Y Wang, X Li, L Xu, JM Meldrim, JK Jhothiraman, S Luo US Patent App. 17/823,472, 2024 | | 2024 |
| STRESS MITIGATION FOR THREE-DIMENSIONAL METAL CONTACTS CS Tiwari, JK Jhothiraman, R Narulkar, N Chakravarty, P Zheng, H Iuchi US Patent App. 18/234,111, 2024 | | 2024 |
| Memory Circuitry And Method Used In Forming Memory Circuitry JK Jhothiraman, C Tiwari US Patent App. 17/944,343, 2024 | | 2024 |
| Integrated Assemblies Which Include Stacked Memory Decks, and Methods of Forming Integrated Assemblies JD Hopkins, J Dorhout, N Bandaru, D Fazil, NM Lomeli, JK Jhothiraman, ... US Patent App. 18/218,762, 2024 | | 2024 |
| Memory Circuitry And Method Used In Forming Memory Circuitry JK Jhothiraman US Patent App. 17/851,393, 2023 | | 2023 |
| Electronic devices comprising a compressive dielectric material, and related systems and methods JK Jhothiraman, R Narulkar, CS Tiwari US Patent App. 17/664,385, 2023 | | 2023 |
Farhang ShadmanProfessor, University of ArizonaVerified email at erc.arizona.edu
