Farrukh Hijaz
Farrukh Hijaz
Facebook Reality Labs
Verified email at uconn.edu
Title
Cited by
Cited by
Year
Crono: A benchmark suite for multithreaded graph algorithms executing on futuristic multicores
M Ahmad, F Hijaz, Q Shi, O Khan
2015 IEEE International Symposium on Workload Characterization, 44-55, 2015
1142015
Survey of fall detection and daily activity monitoring techniques
F Hijaz, N Afzal, T Ahmad, O Hasan
2010 International Conference on Information and Emerging Technologies, 1-6, 2010
672010
Accelerating graph and machine learning workloads using a shared memory multicore architecture with auxiliary support for in-hardware explicit messaging
H Dogan, F Hijaz, M Ahmad, B Kahne, P Wilson, O Khan
2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2017
232017
A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages
F Hijaz, Q Shi, O Khan
2013 IEEE 31st International Conference on Computer Design (ICCD), 85-92, 2013
152013
Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication
F Hijaz, B Kahne, P Wilson, O Khan
2015 IEEE International Conference on Networking, Architecture and Storage …, 2015
132015
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores
O Khan, H Hoffmann, M Lis, F Hijaz, A Agarwal, S Devadas
2011 IEEE 29th International Conference on Computer Design (ICCD), 411-418, 2011
112011
Rethinking Last-Level Cache Management for Multicores Operating at Near-Threshold Voltages
F Hijaz, O Khan
Second Workshop on Near-threshold Computing, 2014
92014
Towards efficient dynamic data placement in NoC-based multicores
Q Shi, F Hijaz, O Khan
2013 IEEE 31st International Conference on Computer Design (ICCD), 369-376, 2013
82013
NUCA-L1: A non-uniform access latency level-1 cache architecture for multicores operating at near-threshold voltages
F Hijaz, O Khan
ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 1-28, 2014
72014
Locality-aware data replication in the last-level cache for large scale multicores
F Hijaz, Q Shi, G Kurian, S Devadas, O Khan
The Journal of Supercomputing 72 (2), 718-752, 2016
62016
Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads
M Ahmad, SK Haider, F Hijaz, M van Dijk, O Khan
Proceedings of the Fourth Workshop on Hardware and Architectural Support for …, 2015
62015
LDAC: Locality-aware data access control for large-scale multicore cache hierarchies
Q Shi, G Kurian, F Hijaz, S Devadas, O Khan
ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-28, 2016
52016
Low-latency mechanisms for near-threshold operation of private caches in shared memory multicores
F Hijaz, Q Shi, O Khan
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture …, 2012
42012
Performance by retaining high locality data in higher level cache memory
F Hijaz, G Patsilaras
US Patent 10,503,656, 2019
22019
Reuse Aware Cache Line Insertion And Victim Selection In Large Cache Memory
F Hijaz, G Patsilaras
US Patent App. 15/695,732, 2019
22019
M-map: Multi-factor memory authentication for secure embedded processors
SK Haider, M Ahmad, F Hijaz, A Patni, E Johnson, M Seita, O Khan, ...
2015 33rd IEEE International Conference on Computer Design (ICCD), 471-474, 2015
22015
Accelerating Communication in Single-chip Shared Memory Many-core Processors
F Hijaz, B Kahne, P Wilson, O Khan
Sixth Annual Boston Area Architecture Workshop, 2015
22015
Automatic cache coherency for page table data
AE Turner, F Hijaz, B Rychlik
US Patent 10,339,058, 2019
12019
Reducing Clean Evictions In An Exclusive Cache Memory Hierarchy
F Hijaz
US Patent App. 15/709,960, 2019
12019
Performance By Retaining High Locality Data In Higher Level Cache Memory
F Hijaz, G Patsilaras
US Patent App. 16/565,882, 2020
2020
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