| A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane, ... 2014 IEEE international electron devices meeting, 3.7. 1-3.7. 3, 2014 | 755 | 2014 |
| A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57/spl mu/m/sup 2/SRAM cell P Bai, C Auth, S Balakrishnan, M Bost, R Brain, V Chikarmane, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 382 | 2004 |
| High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors P Packan, S Akbar, M Armstrong, D Bergstrom, M Brazier, H Deshpande, ... 2009 IEEE international electron devices meeting (IEDM), 1-4, 2009 | 287 | 2009 |
| A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2SRAM cell size in a 291Mb array S Natarajan, M Armstrong, M Bost, R Brain, M Brazier, CH Chang, ... 2008 IEEE International Electron Devices Meeting, 1-3, 2008 | 286 | 2008 |
| Self-heat reliability considerations on Intel's 22nm Tri-Gate technology C Prasad, L Jiang, D Singh, M Agostinelli, C Auth, P Bai, T Eiles, J Hicks, ... 2013 IEEE International Reliability Physics Symposium (IRPS), 5D. 1.1-5D. 1.5, 2013 | 117 | 2013 |
| An advanced low power, high performance, strained channel 65nm technology S Tyagi, C Auth, P Bai, G Curello, H Deshpande, S Gannavaram, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 107 | 2005 |
| Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing K Fischer, M Agostinelli, C Allen, D Bahr, M Bost, P Charvat, ... 2015 IEEE International Interconnect Technology Conference and 2015 IEEE …, 2015 | 78 | 2015 |
| Transistor aging and reliability in 14nm tri-gate technology S Novak, C Parker, D Becher, M Liu, M Agostinelli, M Chahal, P Packan, ... 2015 IEEE International Reliability Physics Symposium, 2F. 2.1-2F. 2.5, 2015 | 75 | 2015 |
| A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors CH Jan, P Bai, J Choi, G Curello, S Jacobs, J Jeong, K Johnson, D Jones, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 60-63, 2005 | 66 | 2005 |
| On-chip capacitors and methods of assembling same MA Childs, KJ Fischer, SS Natarajan US Patent 9,627,312, 2017 | 61 | 2017 |
| A classifier neural net with complex-valued weights and square-law nonlinearities D Casasent, S Natarajan Neural Networks 8 (6), 989-998, 1995 | 55 | 1995 |
| Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures C Prasad, M Agostinelli, J Hicks, S Ramey, C Auth, K Mistry, S Natarajan, ... 2014 IEEE International Reliability Physics Symposium, 6A. 5.1-6A. 5.7, 2014 | 53 | 2014 |
| Gas-induced variation in the dielectric properties of carbon nanotube bundles for selective sensing F Picaud, R Langlet, M Arab, M Devel, C Girardet, S Natarajan, S Chopra, ... Journal of Applied Physics 97 (11), 2005 | 53 | 2005 |
| High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology MD Giles, NA Radhakrishna, D Becher, A Kornfeld, K Maurice, S Mudanai, ... 2015 Symposium on VLSI Technology (VLSI Technology), T150-T151, 2015 | 52 | 2015 |
| Transistor with strain-inducing structure in channel SM Cea, R Soman, R Nagisetty, S Tyagi, S Natarajan US Patent 7,019,326, 2006 | 41 | 2006 |
| IEDM Tech. Dig. S Natarajan, M Armstrong, M Bost, R Brain, M Brazier, CH Chang IEDM Tech. Dig 3, 1-3.7, 2008 | 39 | 2008 |
| Ultra-low power 90nm 6T SRAM cell for wireless sensor network applications D Ho, K Iniewski, S Kasnavi, A Ivanov, S Natarajan 2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006 | 26 | 2006 |
| 2nm node: Benchmarking FinFET vs nano-slab transistor architectures for artificial intelligence and next gen smart mobile devices SC Song, B Colombeau, M Bauer, V Moroz, XW Lin, P Asenov, ... 2019 Symposium on VLSI Technology, T206-T207, 2019 | 21 | 2019 |
| A 14 nm logic technology featuring 2 S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane IEDM Tech. Dig, 3.7, 2015 | 19 | 2015 |
| IEDM Tech. Dig. P Packan, S Akbar, M Armstrong, D Bergstrom, M Brazier, H Deshpande IEDM Tech. Dig, 959-662, 2009 | 18 | 2009 |
