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Paul Besser
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Texture analysis of damascene-fabricated Cu lines by x-ray diffraction and electron backscatter diffraction and its impact on electromigration performance
L Vanasupa, YC Joo, PR Besser, S Pramanick
Journal of Applied Physics 85 (5), 2583-2590, 1999
1591999
Mosfets incorporating nickel germanosilicided gate and methods for their formation
EN Paton, Q Xiang, PR Besser, MR Lin, MV Ngo, HH Wang
US Patent 6,787,864, 2004
1332004
Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
MS Buynoski, PR Besser, PL King, EN Paton, Q Xiang
US Patent 6,465,334, 2002
1232002
In situ scanning electron microscopy observation of the dynamic behavior of electromigration voids in passivated aluminum lines
PR Besser, MC Madden, PA Flinn
Journal of applied physics 72 (8), 3792-3797, 1992
1111992
Microstructural characterization of inlaid copper interconnect lines
PR Besser, E Zschech, W Blum, D Winter, R Ortega, S Rose, M Herrick, ...
Journal of Electronic Materials 30, 320-330, 2001
1042001
Pre-cleaning for silicidation in an SMOS process
EN Paton, PR Besser, Q Xiang
US Patent 6,811,448, 2004
1002004
Method and apparatus for controlling the thickness of a selective epitaxial growth layer
PR Besser, EN Paton, GE William
US Patent 7,402,207, 2008
992008
Selective deposition process for passivating top interface of damascene-type Cu interconnect lines
PR Besser, DM Erb, S Lopatin
US Patent 6,455,425, 2002
982002
Damascene NiSi metal gate high-k transistor
Q Xiang, PR Besser, MS Buynoski, JC Foster, PL King, EN Paton
US Patent 6,475,874, 2002
972002
An x-ray method for direct determination of the strain state and strain relaxation in micron-scale passivated metallization lines during thermal cycling
PR Besser, S Brennan, JC Bravman
Journal of materials research 9 (1), 13-24, 1994
851994
Scalability of strained-Si nMOSFETs down to 25 nm gate length
JS Goo, Q Xiang, Y Takamura, H Wang, J Pan, F Arasnia, EN Paton, ...
IEEE Electron Device Letters 24 (5), 351-353, 2003
822003
Self-aligned CoSi2 for 0.18 mm and below
K Maex, A Lauwers, P Besser, E Kondoh, M de Potter de ten Broeck, ...
IEEE Transactions on Electron Devices 46 (7), 1545-1550, 1999
821999
Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors
MS Buynoski, PR Besser, Q Xang, PL King, EN Paton
US Patent 6,300,203, 2001
782001
Deposition of a conductor in a via hole or trench
PR Besser, JA Iacoponi, R Alvis
US Patent 5,918,149, 1999
781999
Band offset induced threshold variation in strained-Si nMOSFETs
JS Goo, Q Xiang, Y Takamura, F Arasnia, EN Paton, P Besser, J Pan, ...
IEEE Electron Device Letters 24 (9), 568-570, 2003
722003
Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines
SK Pangrle, PR Besser, M Van Ngo
US Patent 6,174,743, 2001
722001
Semiconductor with tensile strained substrate and method of making the same
MV Ngo, PR Besser, MR Lin, HH Wang
US Patent 7,001,837, 2006
702006
Method to control mechanical stress of copper interconnect line using post-plating copper anneal
PR Besser
US Patent 6,368,967, 2002
682002
Gate dielectric quality for replacement metal gate transistors
J Pan, P Besser, CMC Woo, M Van Ngo, J Yin
US Patent 6,830,998, 2004
612004
Manufacturing capping layer for the fabrication of cobalt salicide structures
PR Besser, RW Cheung, R Chen
US Patent 5,970,370, 1999
591999
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