| A 1.2 V 30nm 1.6 Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme YC Bae, JY Park, SJ Rhee, SB Ko, Y Jeong, KS Noh, Y Son, J Youn, ... 2012 IEEE International Solid-State Circuits Conference, 44-46, 2012 | 47 | 2012 |
| Delay locked loop circuits and methods of operation thereof YG Chu, J Lee US Patent 6,285,225, 2001 | 30 | 2001 |
| A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm … KC Chun, YG Chu, JS Heo, TS Kim, S Kim, HK Yang, MJ Kim, CK Lee, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 206-208, 2018 | 23 | 2018 |
| Semiconductor memory device including standby mode for reducing current consumption of delay locked loop YG Chu, KC Lee US Patent 6,678,206, 2004 | 20 | 2004 |
| Integrated circuit devices having synchronized signal generators therein YG Chu, J Lee US Patent 6,222,411, 2001 | 11 | 2001 |
| Synchronous semiconductor memory device YG Chu US Patent 7,420,871, 2008 | 9 | 2008 |
| Synchronous semiconductor memory device YG Chu US Patent 7,420,871, 2008 | 9 | 2008 |
| Circuit and method for transforming data input/output format in parallel bit test JH Ryu, CS Shin, YG Chu US Patent 6,909,650, 2005 | 8 | 2005 |
| Circuit and method for transforming data input/output format in parallel bit test J Ryu, C Shin, YG Chu US Patent 6,909,650, 2005 | 8 | 2005 |
| Precharge method of semiconductor memory device and semiconductor memory device using the same YG Chu, W Jeong US Patent 8,315,118, 2012 | 5 | 2012 |
| Precharge method of semiconductor memory device and semiconductor memory device using the same YG Chu, W Jeong US Patent 8,315,118, 2012 | 5 | 2012 |
| Semiconductor device including option pads for determining an operating structure thereof, and a system having the same YG Chu, HS Kang, SB Ko, SJ Rhee US Patent 9,390,772, 2016 | 3 | 2016 |
| Semiconductor test circuit H Lee, YG Chu US Patent 7,221,170, 2007 | 3 | 2007 |
| Semiconductor test circuit H Lee, YG Chu US Patent 7,221,170, 2007 | 3 | 2007 |
| Semiconductor memory device comprising two rows of pads DY Kim, WI Bae, YG Chu, JH Kim US Patent 7,580,294, 2009 | 2 | 2009 |
| Semiconductor memory device comprising two rows of pads D Kim, W Bae, YG Chu, JH Kim US Patent 7,580,294, 2009 | 2 | 2009 |
| Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device GY Kim, S Byun, YG Chu, S Park US Patent 7,433,252, 2008 | 2 | 2008 |
| Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device GY Kim, S Byun, YG Chu, S Park US Patent 7,433,252, 2008 | 2 | 2008 |
| Semiconductor memory device with operation environment information storing circuit and command storing function C Kim, M Kim, Y Chu, S Ko US Patent 9,940,046, 2018 | 1 | 2018 |
| Semiconductor memory device with operation environment information storing circuit and command storing function C Kim, M Kim, Y Chu, S Ko US Patent 9,940,046, 2018 | 1 | 2018 |
