关注
Ramon Matas
Ramon Matas
Principal engineer @ nvidia
在 nvidia.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
Federated learning based on dynamic regularization
DAE Acar, Y Zhao, RM Navarro, M Mattina, PN Whatmough, V Saligrama
arXiv preprint arXiv:2111.04263, 2021
6512021
Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers
C Banbury, C Zhou, I Fedorov, R Matas, U Thakker, D Gope, ...
Proceedings of machine learning and systems 3, 517-532, 2021
2312021
Debiasing model updates for improving personalized federated training
DAE Acar, Y Zhao, R Zhu, R Matas, M Mattina, P Whatmough, ...
International conference on machine learning, 21-31, 2021
622021
Apparatus and method for partitioning a shared cache of a chip multi-processor
M Mattina, A Juan-Hormigo, J Emer, R Matas-Navarro
US Patent 7,558,920, 2009
502009
Collapsible linear blocks for super-efficient super resolution
K Bhardwaj, M Milosavljevic, L O'Neil, D Gope, R Matas, A Chalfin, ...
Proceedings of Machine Learning and Systems 4, 529-547, 2022
372022
Performing memory accesses using memory context information
R Matas
US Patent 8,521,944, 2013
202013
Simulating a chip multiprocessor with a symmetric multiprocessor
KC Barr, R Matas-Navarro, C Weaver, T Juan, J Emer
Boston Area Architecture Workshop, 2005
182005
UDC: Unified DNAS for compressible TinyML models
I Fedorov, R Matas, H Tann, C Zhou, M Mattina, P Whatmough
arXiv preprint arXiv:2201.05842, 2022
132022
Stateless capture of data linear addresses during precise event based sampling
R Gramunt, R Matas, BC Chaffin, NS Moyer, R Padmanabhan, AP Suprun, ...
US Patent 9,652,237, 2017
92017
Udc: Unified dnas for compressible tinyml models for neural processing units
I Fedorov, R Matas, H Tann, C Zhou, M Mattina, P Whatmough
Advances in Neural Information Processing Systems 35, 18456-18471, 2022
82022
Reset of processing core in multi-core processing system
SS Chang, A Thakur, R Sundararaman, R Matas
US Patent 9,208,124, 2015
82015
Dynamic partitioning of execution resources
JF Duluk Jr, L Durant, RM Navarro, A Menezes, J Tuckey, G Hirota, ...
US Patent 11,307,903, 2022
42022
Federated learning based on dynamic regularization
V Saligrama, DAE Acar, PN Whatmough, R Matas, M Mattina, Y Zhao
22022
Resolving memory accesses crossing cache line boundaries
R Matas, CL Chan, AP Suprun, A Kesiraju
US Patent 10,318,427, 2019
22019
Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit
SS Chang, A Thakur, R Sundararaman, R Matas, JS Lawlor, RF Netting
US Patent 9,372,816, 2016
22016
Initialization of multi-core processing system
SS Chang, A Thakur, RC Sundararaman, R Matas
US Patent 9,367,329, 2016
22016
PerfSAGE: Generalized Inference Performance Predictor for Arbitrary Deep Learning Models on Edge Devices
Y Chai, D Tripathy, C Zhou, D Gope, I Fedorov, R Matas, D Brooks, ...
arXiv preprint arXiv:2301.10999, 2023
12023
Stateless capture of data linear addresses during precise event based sampling
R Gramunt, R Matas, BC Chaffin, NS Moyer, R Padmanabhan, AP Suprun, ...
US Patent 10,175,986, 2019
12019
Memory fault suppression via re-execution and hardware FSM
R Matas, R Gramunt, CL Chan, BC Chaffin, A Kesiraju, JC Hall, J Corbal
US Patent 9,715,432, 2017
12017
Method and apparatus to share modified data without write-back in a shared-memory many-core system
R Sundararaman, JC Mejia, OM Rosell, J Antonio, R Matas
US Patent App. 13/731,584, 2014
12014
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