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yc chou
yc chou
Macronix International Co Ltd
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Year
Comprehensive scaling study on 3D cross-point PCM toward 1Znm node for SCM applications
WC Chien, HY Ho, CW Yeh, CH Yang, HY Cheng, W Kim, IT Kuo, ...
2019 Symposium on VLSI Technology, T60-T61, 2019
242019
Si incorporation into AsSeGe chalcogenides for high thermal stability, high endurance and extremely low Vth drift 3D stackable cross-point memory
HY Cheng, IT Kuo, WC Chien, CW Yeh, YC Chou, N Gong, L Gignac, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
172020
A no-verification multi-level-cell (MLC) operation in cross-point OTS-PCM
N Gong, W Chien, Y Chou, C Yeh, N Li, H Cheng, C Cheng, I Kuo, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
162020
Optimizing AsSeGe Chalcogenides by Dopants for Extremely Low IOFF, High Endurance and Low Vth Drift 3D Crosspoint Memory
HY Cheng, WC Chien, IT Kuo, CH Yang, YC Chou, RL Bruce, EK Lai, ...
2021 IEEE International Electron Devices Meeting (IEDM), 28.6. 1-28.6. 4, 2021
122021
Memory and operation method therefor
HY Ho, CH Hung, YC Chou
US Patent 8,094,494, 2012
42012
Endurance evaluation on OTS-PCM device using constant current stress scheme
WC Chien, LM Gignac, YC Chou, CH Yang, N Gong, HY Ho, CW Yeh, ...
2022 IEEE International Reliability Physics Symposium (IRPS), P7-1-P7-4, 2022
22022
Leakage current compensation in crossbar array
YC Chou, YF Lin, HY Ho
US Patent 11,049,557, 2021
22021
Device Study on OTS-PCM for Persistent Memory Application: IBM/Macronix Phase Change Memory Joint Project
WC Chien, LM Gignac, YC Chou, CH Yang, N Gong, HY Ho, CW Yeh, ...
2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM …, 2022
12022
Memory circuit with leakage current blocking mechanism and memory device having the memory circuit
TY Wang, YC Chou, CH Hung
US Patent 11,842,769, 2023
2023
Sensing module, memory device, and sensing method applied to identify un-programmed/programmed state of non-volatile memory cell
YC Chou, TY Wang, CH Hung
US Patent App. 17/705,469, 2023
2023
Phase change memory apparatus and read control method to reduce read disturb and sneak current phenomena
YF Lin, YC Chou, HY Ho
US Patent 10,297,316, 2019
2019
Memory and operation method therefor
HY Ho, CH Hung, YC Chou
US Patent 8,456,906, 2013
2013
Using FIR Neural Network to Supplement the FDTD Simulation of Planar Circuits
YC Chou, CW Kuo
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