| A 0.35–0.5-V 18–152 MHz digitally controlled relaxation oscillator with adaptive threshold calibration in 65-nm CMOS Y Zhang, W Rhee, T Kim, H Park, Z Wang IEEE Transactions on Circuits and Systems II: Express Briefs 62 (8), 736-740, 2015 | 32 | 2015 |
| A reconfigurable architecture using a flexible LO modulator to unify high-sensitivity signal reception and compressed-sampling wideband signal detection T Haque, M Bajor, Y Zhang, J Zhu, ZA Jacobs, RB Kettlewell, J Wright, ... IEEE Journal of Solid-State Circuits 53 (6), 1577-1591, 2018 | 23 | 2018 |
| An out-of-band IM3 cancellation technique using a baseband auxiliary path in wideband LNTA-based receivers Y Zhang, J Zhu, PR Kinget IEEE Transactions on Microwave Theory and Techniques 66 (6), 2580-2591, 2018 | 16 | 2018 |
| 11.4 A high-accuracy multi-phase injection-locked 8-phase 7GHz clock generator in 65nm with 7b phase interpolators for high-speed data links Z Wang, Y Zhang, Y Onizuka, PR Kinget 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 186-188, 2021 | 14 | 2021 |
| Multi-phase clock generation for phase interpolation with a multi-phase, injection-locked ring oscillator and a quadrature DLL Z Wang, Y Zhang, Y Onizuka, PR Kinget IEEE Journal of Solid-State Circuits 57 (6), 1776-1787, 2021 | 10 | 2021 |
| A direct RF-to-information converter for reception and wideband interferer detection employing pseudo-random LO modulation T Haque, M Bajor, Y Zhang, J Zhu, Z Jacobs, R Kettlewell, J Wright, ... 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 268-271, 2017 | 8 | 2017 |
| A 0.6 V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS Y Zhang, X Liu, W Rhee, H Jiang, Z Wang 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 8 | 2017 |
| An FTNC receiver with+ 32.5 dBm effective OB-IIP3 using baseband IM3 cancellation Y Zhang, J Zhu, PR Kinget 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 3-6, 2017 | 4 | 2017 |
| A 0.55 V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS Y Zhang, W Rhee, Z Wang, T Kim, H Park 2015 IEEE International Symposium on Radio-Frequency Integration Technology …, 2015 | 4 | 2015 |
| Analysis of injection-locked ring oscillators for quadrature clock generation in wireline or optical transceivers Y Zhang, Z Wang, PR Kinget IEEE Transactions on Circuits and Systems I: Regular Papers 69 (8), 3074-3082, 2022 | 1 | 2022 |
| Design of power-efficient optical transceivers and design of high-linearity wireless wideband receivers Y Zhang Columbia University, 2021 | 1 | 2021 |
| A 1.6 Mb/s 3.75–4.25 GHz chirp-UWB transceiver with enhanced spectral efficiency in 0.18 μm CMOS Y Li, F Chen, D Liu, X Li, Y Li, Y Zhang, Z Wang, W Rhee, Z Wang 2014 IEEE International Symposium on Radio-Frequency Integration Technology, 1-3, 2014 | 1 | 2014 |
| Circuits and methods for multi-phase clock generators and phase interpolators Z Wang, Y Zhang, P Kinget US Patent 20,220,244,755, 2022 | | 2022 |
| The tradeoff between noise, data rate, and power consumption of transimpedance amplifiers for optical receivers Y Zhang, PR Kinget Analog Integrated Circuits and Signal Processing 108 (2), 437-446, 2021 | | 2021 |
| Dynamic multiphase injection-locked phase rotator for electro-optical transceiver Y Zhang, RK Nandwana, K Lakshmikumar US Patent US11063595B1, 2021 | | 2021 |
