Chemical mechanical polishing for hybrid bonding GG Fountain Jr, C Mandalapu, CE Uzoh, JA Theil US Patent 10,840,205, 2020 | 106 | 2020 |
Post cmp processing for hybrid bonding GG Fountain Jr, G Gao, C Mandalapu US Patent App. 16/511,394, 2020 | 65 | 2020 |
DBI to Si bonding for simplified handle wafer C Mandalapu, GG Fountain Jr, G Gao US Patent 10,964,664, 2021 | 63 | 2021 |
Scaling package interconnects below 20µm pitch with hybrid bonding G Gao, L Mirkarimi, G Fountain, L Wang, C Uzoh, T Workman, G Guevara, ... 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 314-322, 2018 | 54 | 2018 |
3D packaging for heterogeneous integration R Agarwal, P Cheng, P Shah, B Wilkerson, R Swaminathan, J Wuu, ... 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 1103-1107, 2022 | 44 | 2022 |
Design, fabrication, and testing of a liquid cooling platform for high power 3D-ICs C Mandalapu, I Abdel-Motaleb, S Hong, R Patti 2019 8th International Symposium on Next Generation Electronics (ISNE), 1-4, 2019 | 7 | 2019 |
Chemical mechanical polishing for hybrid bonding GG Fountain Jr, C Mandalapu, CE Uzoh, JA Theil US Patent 11,552,041, 2023 | 5 | 2023 |
Mechanical strength characterization of direct bond interfaces for 3D-IC and MEMS applications B Lee, R Katkar, G Gao, G Fountain, S Lee, L Wang, C Mandalapu, ... 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 954-961, 2018 | 5 | 2018 |
Techniques for joining dissimilar materials in microelectronics GG Fountain Jr, C Mandalapu, LW Mirkarimi US Patent 11,664,357, 2023 | 2 | 2023 |
Techniques for joining dissimilar materials in microelectronics GG Fountain Jr, C Mandalapu, LW Mirkarimi US Patent App. 18/300,306, 2023 | 1 | 2023 |
12 Applications of Hybrid C Mandalapu, J Wuu, R Swaminathan, L Wang Direct Copper Interconnection for Advanced Semiconductor Technology, 428, 2024 | | 2024 |
Dbi to si bonding for simplified handle wafer C Mandalapu, GG Fountain Jr, G Gao US Patent App. 18/464,982, 2024 | | 2024 |
PARTITIONING WAFER PROCESSING AND HYBRID BONDING OF LAYERS FORMED ON DIFFERENT WAFERS FOR A SEMICONDUCTOR ASSEMBLY R Agarwal, CS Mandalapu, R Swaminathan US Patent App. 17/896,746, 2024 | | 2024 |
Double side transistors on same silicon wafer CS Mandalapu, R Agarwal, R Swaminathan, RT Schultz US Patent App. 17/873,591, 2024 | | 2024 |
Applications of Hybrid Bonding and Chiplets for Heterogeneous Integration C Mandalapu, J Wuu, R Swaminathan, L Wang Direct Copper Interconnection for Advanced Semiconductor Technology, 428-445, 2024 | | 2024 |
DBI to SI bonding for simplified handle wafer C Mandalapu, GG Fountain Jr, G Gao US Patent 11,791,307, 2023 | | 2023 |
Chemical mechanical polishing for hybrid bonding GG Fountain Jr, C Mandalapu, CE Uzoh, JA Theil US Patent App. 18/067,617, 2023 | | 2023 |
Access Line Having a Resistive Layer for Memory Cell Access SV Sateesh Talasila, Chandrasekhar Mandalapu, Robert Douglas Cassel ... US Patent App. 20,230/069,190, 2023 | | 2023 |
Design and fabrication of a testing platform for liquid cooling of 3D integrated circuits C Mandalapu Northern Illinois University, 2014 | | 2014 |