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Yuzhe Ma
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Recent advances in convolutional neural network acceleration
Q Zhang, M Zhang, T Chen, Z Sun, Y Ma, B Yu
Neurocomputing 323, 37-51, 2019
2202019
Layout hotspot detection with feature tensor generation and deep biased learning
H Yang, J Su, Y Zou, Y Ma, B Yu, EFY Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
1032018
GAN-OPC: Mask optimization with lithography-guided generative adversarial nets
H Yang, S Li, Z Deng, Y Ma, B Yu, EFY Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
822019
High performance graph convolutional networks with applications in testability analysis
Y Ma, H Ren, B Khailany, H Sikka, L Luo, K Natarajan, B Yu
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
572019
Machine learning for electronic design automation: A survey
G Huang, J Hu, Y He, J Liu, M Ma, Z Shen, J Wu, Y Xu, H Zhang, K Zhong, ...
ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (5 …, 2021
452021
Clock-aware ultrascale FPGA placement with machine learning routability prediction
CW Pui, G Chen, Y Ma, EFY Young, B Yu
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 929-936, 2017
402017
SRAF insertion via supervised dictionary learning
H Geng, W Zhong, H Yang, Y Ma, J Mitra, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
202019
Cross-layer optimization for high speed adders: A pareto driven machine learning approach
Y Ma, S Roy, J Miao, J Chen, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
192018
Adversarial perturbation attacks on ML-based CAD: A case study on CNN-based lithographic hotspot detection
K Liu, H Yang, Y Ma, B Tan, B Yu, EFY Young, R Karri, S Garg
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (5 …, 2020
182020
A unified framework for simultaneous layout decomposition and mask optimization
Y Ma, W Zhong, S Hu, JR Gao, J Kuang, J Miao, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
172020
A Unified Approximation Framework for Compressing and Accelerating Deep Neural Networks
Y Ma, R Chen, W Li, F Shang, W Yu, M Cho, B Yu
arXiv preprint arXiv:1807.10119, 2018
142018
SD-PUF: Spliced digital physical unclonable function
J Miao, M Li, S Roy, Y Ma, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
142017
VLSI mask optimization: From shallow to deep learning
H Yang, W Zhong, Y Ma, H Geng, R Chen, W Chen, B Yu
Integration 77, 96-103, 2021
132021
Understanding graphs in EDA: From shallow to deep learning
Y Ma, Z He, W Li, L Zhang, B Yu
Proceedings of the 2020 International Symposium on Physical Design, 119-126, 2020
112020
DAMO: Deep agile mask optimization for full chip scale
G Chen, W Chen, Q Sun, Y Ma, H Yang, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
102021
Neural-ILT: Migrating ILT to neural networks for mask printability and complexity co-optimization
B Jiang, L Liu, Y Ma, H Zhang, B Yu, EFY Young
2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2020
102020
CAD tool design space exploration via Bayesian optimization
Y Ma, Z Yu, B Yu
2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD), 1-6, 2019
102019
A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders
S Roy, Y Ma, J Miao, B Yu
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
102017
Deep learning-driven simultaneous layout decomposition and mask optimization
W Zhong, S Hu, Y Ma, H Yang, X Ma, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
82021
High-speed adder design space exploration via graph neural processes
H Geng, Y Ma, Q Xu, J Miao, S Roy, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
72021
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