Suman Datta

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Vijaykrishnan NarayananRobert Noll Chair Professor at The Pennsylvania State UniversityVerified email at cse.psu.edu
Kai NiUniversity of Notre DameVerified email at nd.edu
Sumeet GuptaSchool of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
Nikhil ShuklaUniversity of VirginiaVerified email at virginia.edu
Marko RadosavljevicIntel CorporationVerified email at intel.com
Matthew JerryUniversity of Notre Dame / Pennsylvania State UniversityVerified email at nd.edu
Xueqing LiAssociate Professor, Tsinghua UniversityVerified email at tsinghua.edu.cn
Ahmedullah AzizAssistant Professor, University of Tennessee, KnoxvilleVerified email at utk.edu
Darrell G. SchlomCornell UniversityVerified email at cornell.edu
Prof. Mantu HudaitAssoc. Prof. of ECE, Virginia Tech; Past: Intel Corporation, Ohio State U, IISc-Bangalore, IIT-KGPVerified email at vt.edu
Dheeraj MohataSenior Integration Engineer, GCS IncVerified email at gcsincorp.com
Benjamin GrisafeUniversity of Notre DameVerified email at nd.edu
Huichu LiuIntel Labs, Intel CorporationVerified email at intel.com
Joshua A. RobinsonProf. MatSE; Center for 2DLM; ATOMIC; 2D Crystal Consort.; The Pennsylvania State UniversityVerified email at psu.edu
Himanshu MadanIntel, PennState UniversityVerified email at intel.com
vinay saripalliPhD in computer Science and Engineering, Penn State UniversityVerified email at psu.edu
Ram Krishna GhoshAssistant Professor, ECE, IIIT-DelhiVerified email at iiitd.ac.in
Roman Engel-HerbertDirektor, Paul-Drude-Institut für Festkörperelektronik, Leibniz Institut im Foschungsverbund BerlinVerified email at pdi-berlin.de
Ashish AgrawalDevcie Engineer at Components Research, Intel CorporationVerified email at intel.com
Abhinav PariharColumbia UniversityVerified email at columbia.edu

Suman Datta

Joseph M. Pettit Chair Professor

Verified email at gatech.edu - Homepage

Georgia Tech


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Benchmarking nanotechnology for high-performance and low-power logic transistor applications R Chau, S Datta, M Doczy, B Doyle, B Jin, J Kavalieros, A Majumdar, ... IEEE transactions on nanotechnology 4 (2), 153-158, 2005	878	2005
High-/spl kappa//metal-gate stack and its MOSFET characteristics R Chau, S Datta, M Doczy, B Doyle, J Kavalieros, M Metz IEEE Electron Device Letters 25 (6), 408-410, 2004	741*	2004
Two-dimensional gallium nitride realized via graphene encapsulation ZY Al Balushi, K Wang, RK Ghosh, RA Vilá, SM Eichfeld, JD Caldwell, ... Nature materials 15 (11), 1166-1171, 2016	711	2016
High performance fully-depleted tri-gate CMOS transistors BS Doyle, S Datta, M Doczy, S Hareland, B Jin, J Kavalieros, T Linton, ... IEEE Electron Device Letters 24 (4), 263-265, 2003	672	2003
Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta US Patent 7,358,121, 2008	519	2008
Ferroelectric FET analog synapse for acceleration of deep neural network training M Jerry, PY Chen, J Zhang, P Sharma, K Ni, S Yu, S Datta 2017 IEEE international electron devices meeting (IEDM), 6.2. 1-6.2. 4, 2017	514	2017
Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta, SA Hareland US Patent 6,858,478, 2005	500	2005
The future of ferroelectric field-effect transistor technology AI Khan, A Keshavarzi, S Datta Nature Electronics 3 (10), 588-597, 2020	489	2020
The era of hyper-scaling in electronics S Salahuddin, K Ni, S Datta Nature electronics 1 (8), 442-450, 2018	486	2018
Integrated nanoelectronics for the future R Chau, B Doyle, S Datta, J Kavalieros, K Zhang Nature materials 6 (11), 810-812, 2007	484	2007
Atomic layer deposition of high dielectric constant gate dielectrics M Metz, C Boyd, M Kuhn, S Datta, J Kavalieros, M Doczy, J Brask, R Chau US Patent App. 10/943,693, 2006	443	2006
Atomically thin resonant tunnel diodes built from synthetic van der Waals heterostructures YC Lin, RK Ghosh, R Addou, N Lu, SM Eichfeld, H Zhu, MY Li, X Peng, ... Nature communications 6 (1), 7311, 2015	432	2015
A steep-slope transistor based on abrupt electronic phase transition N Shukla, AV Thathachary, A Agrawal, H Paik, A Aziz, DG Schlom, ... Nature communications 6 (1), 7812, 2015	376	2015
Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout B Doyle, B Boyanov, S Datta, M Doczy, S Hareland, B Jin, J Kavalieros, ... 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2003	363	2003
2018 IEEE Int. Electron Devices Meeting (IEDM) Z Wang, B Crafton, J Gomez, R Xu, A Luo, Z Krivokapic, L Martin, S Datta, ... IEEE 13, 1, 2018	341	2018
Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering J Kavalieros, B Doyle, S Datta, G Dewey, M Doczy, B Jin, D Lionberger, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 50-51, 2006	340	2006
Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication SA Hareland, RS Chau, BS Doyle, R Rios, T Linton, S Datta US Patent 7,820,513, 2010	338	2010
2022 roadmap on neuromorphic computing and engineering DV Christensen, R Dittmann, B Linares-Barranco, A Sebastian, ... Neuromorphic Computing and Engineering 2 (2), 022501, 2022	319	2022
Critical Role of Interlayer in Hf_0.5Zr_0.5O₂Ferroelectric FET Nonvolatile Memory Performance K Ni, P Sharma, J Zhang, M Jerry, JA Smith, K Tapily, R Clark, ... IEEE Transactions on Electron Devices 65 (6), 2461-2469, 2018	316	2018
Method and apparatus for improving stability of a 6T CMOS SRAM cell S Datta, BS Doyle, RS Chau, J Kavalieros, B Zheng, SA Hareland US Patent 6,970,373, 2005	312	2005

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