| Device scaling limits of Si MOSFETs and their application dependencies DJ Frank, RH Dennard, E Nowak, PM Solomon, Y Taur, HSP Wong Proceedings of the IEEE 89 (3), 259-288, 2001 | 2011 | 2001 |
| CMOS scaling into the nanometer regime Y Taur, D Buchanan, W Chen, DJ Frank, KE Ismail, SH Lo, G Sai-Halasz, ... Proceedings of the IEEE 85 (4), 486-504, 1997 | 1287 | 1997 |
| Three-dimensional integrated circuits AW Topol, DC La Tulipe, L Shi, DJ Frank, K Bernstein, SE Steen, A Kumar, ... IBM Journal of Research and Development 50 (4.5), 491-506, 2006 | 903 | 2006 |
| High-performance CMOS variability in the 65-nm regime and beyond K Bernstein, DJ Frank, AE Gattiker, W Haensch, BL Ji, SR Nassif, ... IBM journal of research and development 50 (4.5), 433-449, 2006 | 704 | 2006 |
| Nanoscale cmos HSP Wong, DJ Frank, PM Solomon, CHJ Wann, JJ Welser Proceedings of the IEEE 87 (4), 537-570, 1999 | 688 | 1999 |
| Quasi-one-dimensional electron states in a split-gate GaAs/AlGaAs heterostructure SE Laux, DJ Frank, F Stern Surface Science 196 (1), 101-106, 1988 | 465 | 1988 |
| Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go? DJ Frank, SE Laux, MV Fischetti Electron Devices Meeting, 1992. IEDM'92. Technical Digest., International …, 1992 | 441 | 1992 |
| Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation HSP Wong, DJ Frank, PM Solomon International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 432 | 1998 |
| Generalized scale length for two-dimensional effects in MOSFETs DJ Frank, Y Taur, HSP Wong Electron Device Letters, IEEE 19 (10), 385-387, 1998 | 431 | 1998 |
| 25 nm CMOS design considerations Y Taur, CH Wann, DJ Frank International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 370 | 1998 |
| Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs) AW Topol, DC La Tulipe, L Shi, SM Alam, DJ Frank, SE Steen, J Vichiconti, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 345 | 2005 |
| Power-constrained CMOS scaling limits DJ Frank IBM Journal of Research and Development 46 (2.3), 235-244, 2002 | 331 | 2002 |
| Highly efficient algorithm for percolative transport studies in two dimensions DJ Frank, CJ Lobb Physical Review B 37 (1), 302, 1988 | 320 | 1988 |
| Toward High-performance digital logic technology with carbon nanotubes GS Tulevski, AD Franklin, D Frank, JM Lobez, Q Cao, H Park, A Afzali, ... ACS nano 8 (9), 8730-8745, 2014 | 316 | 2014 |
| Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode C Dubourdieu, J Bruley, TM Arruda, A Posadas, J Jordan-Sweet, ... Nature nanotechnology 8 (10), 748, 2013 | 284 | 2013 |
| EMPIRICAL FIT TO BAND DISCONTINUITIES AND BARRIER HEIGHTS IN III-V ALLOY SYSTEMS-REPLY S TIWARI, DJ FRANK APPLIED PHYSICS LETTERS 61 (18), 2244-2244, 1992 | 279* | 1992 |
| Empirical fit to band discontinuities and barrier heights in III–V alloy systems S Tiwari, DJ Frank Applied physics letters 60 (5), 630-632, 1992 | 279 | 1992 |
| Methods of forming wiring to transistor and related transistor DJ Frank, DC LaTulipe Jr, SE Steen, AW Topol US Patent App. 14/167,298, 2014 | 253* | 2014 |
| Methods of forming wiring to transistor and related transistor DJ Frank, DC La Tulipe Jr, SE Steen, AW Topol US Patent 7,666,723, 2010 | 250 | 2010 |
| Overlay as the key to drive wafer scale 3D integration SE Steen, D LaTulipe, AW Topol, DJ Frank, K Belote, D Posillico Microelectronic engineering 84 (5-8), 1412-1415, 2007 | 246 | 2007 |
H.-S. Philip WongProfessor of Electrical Engineering, Stanford UniversityVerified email at stanford.edu
