Dongkwan Suh
Dongkwan Suh
Samsung Research, Samsung Electronics
在 的電子郵件地址已通過驗證
Reconfigurable processor and reconfigurable processing method of vector operation using vector lane configuration information
D Suh, HS Yu, SJ Kim
US Patent 9,135,003, 2015
Design space exploration and implementation of a high performance and low area coarse grained reconfigurable processor
D Suh, K Kwon, S Kim, S Ryu, J Kim
2012 International Conference on Field-Programmable Technology, 67-70, 2012
Fused multiply-add apparatus and method
HS Yu, D Suh, SJ Kim, S Kim, Y Lee
US Patent 8,805,915, 2014
Processor including a cache and a scratch pad memory and memory control method thereof
IH Park, RYU Soojung, D Yoo, DK Suh, KIM Jeongwook, CK Jang
US Patent 9,015,451, 2015
Static branch prediction method and code execution method for pipeline processor, and code compiling method for static branch prediction
T Jin, D Suh, SJ Kim
US Patent 8,954,946, 2015
Method of power simulation and power simulator
DK Suh, RYU Soojung, D Yoo, IH Park
US Patent 8,095,806, 2012
Improving energy efficiency of coarse-grain reconfigurable arrays through modulo schedule compression/decompression
H Lee, MS Moghaddam, D Suh, B Egger
ACM Transactions on Architecture and Code Optimization (TACO) 15 (1), 1-26, 2018
NOP compression scheme for high speed DSPs based on VLIW architecture
T Jin, M Ahn, D Yoo, D Suh, Y Choi, DH Kim, S Lee
2014 IEEE International Conference on Consumer Electronics (ICCE), 304-305, 2014
Reconfigurable processor and mini-core of reconfigurable processor
D Suh, SJ Kim, HS Yu, K Kwon, J Park
US Patent 9,330,057, 2016
Cache memory system using temporal locality information and a data storage method
JM Kim, RYU Soojung, D Yoo, DK Suh, KIM Jeongwook
US Patent 8,793,437, 2014
Device and method for processing convolution operation using kernel
K Kim, YH Park, D Suh, K Prasad, DH Kim, SJ Kim, H Cho, HJ Kim
US Patent App. 16/163,772, 2019
Method and device for processing vliw instruction, and method and device for generating instruction for processing vliw instruction
D Suh, SJ Kim, D Kim, T Jin
US Patent App. 15/125,023, 2017
Method and apparatus for controlling reconfigurable processor
D Suh, SJ Kim, CS Park
US Patent App. 15/039,603, 2017
Pre-tracing instructions for CGA coupled processor in inactive mode for execution upon switch to active mode and continuing pre-fetching cache miss instructions
IH Park, D Yoo, DK Suh, RYU Soojung, KIM Jeongwook
US Patent 7,836,277, 2010
Method of managing instruction cache and processor using the method
IH Park, D Yoo, DK Suh, RYU Soojung, KIM Jeongwook
US Patent App. 12/042,868, 2009
Data input/output unit, electronic apparatus, and control methods thereof
J Park, JH Lee, K Kwon, D Suh, JU Cho
US Patent 10,481,867, 2019
Method and apparatus for performing vector operations using look up tables
JU Cho, SJ Kim, D Suh
US Patent 10,409,596, 2019
Reconfigurable processor and operation method therefor
D Suh, K Kwon, YH Park, SW Lee, SJ Kim
US Patent 10,396,797, 2019
Processor and controlling method thereof to process an interrupt
C Im, D Suh, SJ Kim, SW Lee
US Patent 10,318,452, 2019
Processor and control methods thereof
K Kim, YH Park, D Suh, KP Nagaraja, SJ Kim, H Cho, HJ Kim
US Patent App. 16/143,922, 2019
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