| An inverter-based analog front-end for a 56-Gb/s PAM-4 wireline transceiver in 16-nm CMOS K Zheng, Y Frans, SL Ambatipudi, S Asuncion, HT Reddy, K Chang, ... IEEE Solid-State Circuits Letters 1 (12), 249-252, 2018 | 49 | 2018 |
| A 112GB/S PAM4 wireline receiver using a 64-way time-interleaved SAR ADC in 16NM FinFET J Hudner, D Carey, R Casey, K Hearne, PWAF Neto, I Chlis, M Erett, ... 2018 IEEE Symposium on VLSI Circuits, 47-48, 2018 | 35 | 2018 |
| A 112-Gb/s PAM4 transmitter in 16nm FinFET KH Tan, PC Chiang, Y Wang, H Zhao, A Roldan, H Zhao, N Narang, ... 2018 IEEE Symposium on VLSI Circuits, 45-46, 2018 | 32 | 2018 |
