| Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device VGR Vakada, L Kang, MP Ganz, Y Qi, P Khanna, SC Vemula, ... US Patent 8,916,442, 2014 | 13 | 2014 |
| Blanket EPI super steep retrograde well formation without Si recess L Kang, VGR Vakada, MP Ganz, Y Qi, P Khanna, SC Vemula, ... US Patent 9,099,525, 2015 | 7 | 2015 |
| Forming independent-gate finfet with tilted pre-amorphization implantation and resulting device X Wu, JM Van Meer, M Eller, VGR Vakada US Patent App. 14/285,042, 2015 | 5 | 2015 |
| Advanced faraday shield for a semiconductor device Y Liu, V Vakada, J Ciavatti US Patent 9,064,868, 2015 | 5 | 2015 |
| Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures VGR Vakada, L Kang, M Ganz, Y Qi, P Khanna, SB Samavedam, ... US Patent 9,852,954, 2017 | 2 | 2017 |
| Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device VGR Vakada, L Kang, MP Ganz, Y Qi, P Khanna, SC Vemula, ... US Patent 9,099,380, 2015 | 1 | 2015 |
| Method of tailoring silicon trench profile for super steep retrograde well field effect transistor Y Qi, P Khanna, S Samavedam, VG Vakada, MP Ganz, SC Vemula, ... US Patent App. 13/612,032, 2014 | 1 | 2014 |
| Method for forming N-shaped bottom stress liner X Yang, Y Liu, VGR Vakada, J Liu, M Dai US Patent 8,557,668, 2013 | 1 | 2013 |
| Test structures connected with the lowest metallization levels in an interconnect structure M Yang, VGR Vakada, E Maciejewski, B Greene, A Ogino, V Chauhan, ... US Patent 10,796,973, 2020 | | 2020 |
| Test structure leveraging the lowest metallization level of an interconnect structure M Yang, VGR Vakada, E Maciejewski, B Greene, A Ogino, V Chauhan, ... US Patent 10,790,204, 2020 | | 2020 |
| Transistor device structures with retrograde wells in CMOS applications VGR Vakada, L Kang, M Ganz, Y Qi, P Khanna, SB Samavedam, ... US Patent 10,483,172, 2019 | | 2019 |
| Non-planar vertical dual source drift metal-oxide semiconductor (VDSMOS) J Ciavatti, Y Liu, VGR Vakada US Patent 9,601,578, 2017 | | 2017 |
| Blanket EPI super steep retrograde well formation without Si recess L Kang, VGR Vakada, M Ganz, Y Qi, P Khanna, SC Vemula, ... US Patent 9,362,357, 2016 | | 2016 |
| Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures VGR Vakada, L Kang, M Ganz, Y Qi, P Khanna, SB Samavedam, ... US Patent 9,209,181, 2015 | | 2015 |
| Method for forming N-shaped bottom stress liner X Yang, Y Liu, VGR Vakada, J Liu, M Dai US Patent 8,669,616, 2014 | | 2014 |
| Semiconductor device with an oversized local contact as a Faraday shield Y Liu, YW Teh, V Vakada US Patent 8,664,717, 2014 | | 2014 |
