| GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning H Wang, K Wang, J Yang, L Shen, N Sun, HS Lee, S Han 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 214 | 2020 |
| An energy-efficient comparator with dynamic floating inverter amplifier X Tang, L Shen, B Kasap, X Yang, W Shi, A Mukherjee, DZ Pan, N Sun IEEE Journal of Solid-State Circuits 55 (4), 1011-1022, 2020 | 166 | 2020 |
| Modular and reconfigurable wireless e‐tattoos for personalized sensing H Jeong, L Wang, T Ha, R Mitbander, X Yang, Z Dai, S Qiao, L Shen, ... Advanced Materials Technologies 4 (8), 1900117, 2019 | 98 | 2019 |
| A 1-V 0.25- Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor L Shen, N Lu, N Sun IEEE Journal of Solid-State Circuits 53 (3), 896-905, 2018 | 94 | 2018 |
| Wellgan: Generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout B Xu, Y Lin, X Tang, S Li, L Shen, N Sun, DZ Pan Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 71 | 2019 |
| A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, S Li, ... IEEE Journal of Solid-State Circuits 55 (12), 3248-3259, 2020 | 68 | 2020 |
| A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- M Structure W Zhao, S Li, B Xu, X Yang, X Tang, L Shen, N Lu, DZ Pan, N Sun IEEE Journal of Solid-State Circuits 55 (3), 666-679, 2019 | 51 | 2019 |
| A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation J Liu, X Tang, W Zhao, L Shen, N Sun IEEE Journal of Solid-State Circuits 55 (12), 3260-3270, 2020 | 45 | 2020 |
| Towards decrypting the art of analog layout: Placement quality prediction via transfer learning M Liu, K Zhu, J Gu, L Shen, X Tang, N Sun, DZ Pan 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 496-501, 2020 | 43 | 2020 |
| 9.5 a 13.5 b-ENOB second-order noise-shaping SAR with PVT-robust closed-loop dynamic amplifier X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 162-164, 2020 | 42 | 2020 |
| S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity M Liu, W Li, K Zhu, B Xu, Y Lin, L Shen, X Tang, N Sun, DZ Pan 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 193-198, 2020 | 41 | 2020 |
| The challenges and emerging technologies for low-power artificial intelligence IoT systems L Ye, Z Wang, Y Liu, P Chen, H Li, H Zhang, M Wu, W He, L Shen, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (12), 4821-4834, 2021 | 39 | 2021 |
| Low-power SAR ADC design: Overview and survey of state-of-the-art techniques X Tang, J Liu, Y Shen, S Li, L Shen, A Sanyal, K Ragab, N Sun IEEE Transactions on Circuits and Systems I: Regular Papers 69 (6), 2249-2262, 2022 | 37 | 2022 |
| 18.2 a 16fJ/Conversion-step time-domain two-step Capacitance-to-Digital converter X Tang, S Li, L Shen, W Zhao, X Yang, R Williams, J Liu, Z Tan, N Hall, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 296-297, 2019 | 31 | 2019 |
| 16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation J Liu, X Tang, W Zhao, L Shen, N Sun 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 258-260, 2020 | 28 | 2020 |
| Device layer-aware analytical placement for analog circuits B Xu, S Li, CW Pui, D Liu, L Shen, Y Lin, N Sun, DZ Pan Proceedings of the 2019 International Symposium on Physical Design, 19-26, 2019 | 28 | 2019 |
| A two-step ADC with a continuous-time SAR-based first stage L Shen, Y Shen, Z Li, W Shi, X Tang, S Li, W Zhao, M Zhang, Z Zhu, N Sun IEEE Journal of Solid-State Circuits 54 (12), 3375-3385, 2019 | 26 | 2019 |
| NFC-enabled, tattoo-like stretchable biosensor manufactured by “cut-and-paste” method H Jeong, T Ha, I Kuang, L Shen, Z Dai, N Sun, N Lu 2017 39th annual international conference of the IEEE engineering in …, 2017 | 25 | 2017 |
| An 82nW 0.53 pJ/SOP clock-free spiking neural network with 40µs latency for AloT wake-up functions using ultimate-event-driven bionic architecture and computing-in-memory technique Y Liu, Z Wang, W He, L Shen, Y Zhang, P Chen, M Wu, H Zhang, P Zhou, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 372-374, 2022 | 23 | 2022 |
| A Second-Order Purely VCO-Based CT ADC Using a Modified DPLL Structure in 40-nm CMOS Y Zhong, S Li, X Tang, L Shen, W Zhao, S Wu, N Sun IEEE Journal of Solid-State Circuits 55 (2), 356-368, 2019 | 22 | 2019 |
Nan Sun (孙楠)Tsinghua UniversityVerified email at tsinghua.edu.cn
