Yijin Guan
Yijin Guan
Computing Technology Lab, Alibaba DAMO Academy
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Optimizing FPGA-based accelerator design for deep convolutional neural networks
C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong
Proceedings of the 2015 ACM/SIGDA international symposium on field …, 2015
FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates
Y Guan, H Liang, N Xu, W Wang, S Shi, X Chen, G Sun, W Zhang, J Cong
2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017
FPGA-based accelerator for long short-term memory recurrent neural networks
Y Guan, Z Yuan, G Sun, J Cong
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 629-634, 2017
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System
D Niu, S Li, Y Wang, W Han, Z Zhang, Y Guan, T Guan, F Sun, F Xue, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
Blockgnn: Towards efficient gnn acceleration using block-circulant weight matrices
Z Zhou, B Shi, Z Zhang, Y Guan, G Sun, G Luo
2021 58th ACM/IEEE Design Automation Conference (DAC), 1009-1014, 2021
Gnn-pim: A processing-in-memory architecture for graph neural networks
Z Wang, Y Guan, G Sun, D Niu, Y Wang, H Zheng, Y Han
Advanced Computer Architecture: 13th Conference, ACA 2020, Kunming, China …, 2020
Hyperscale fpga-as-a-service architecture for large-scale distributed graph neural network
S Li, D Niu, Y Wang, W Han, Z Zhang, T Guan, Y Guan, H Liu, L Huang, ...
Proceedings of the 49th Annual International Symposium on Computer …, 2022
Using data compression for optimizing FPGA-based convolutional neural network accelerators
Y Guan, N Xu, C Zhang, Z Yuan, J Cong
International workshop on advanced parallel processing technologies, 14-26, 2017
Crane: Mitigating accelerator under-utilization caused by sparsity irregularities in cnns
Y Guan, G Sun, Z Yuan, X Li, N Xu, S Chen, J Cong, Y Xie
IEEE Transactions on Computers 69 (7), 931-943, 2020
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators
Q Zheng, X Li, Y Guan, Z Wang, Y Cai, Y Chen, G Sun, R Huang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022
Instruction processing apparatus, acceleration unit, and server
G Yijin, F Sun, L Liang
US Patent App. 17/717,108, 2022
Accelerating cpu-based sparse general matrix multiplication with binary row merging
Z Du, Y Guan, T Guan, D Niu, H Zheng, Y Xie
IEEE Access 10, 79237-79248, 2022
Computation unit, related apparatus, and method
G Yijin, F Sun, LUO Junwen, H Li, W Bangyan, G Tianchan, Y Zhang
US Patent App. 17/510,217, 2022
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network
L Huang, Z Zhang, S Li, D Niu, Y Guan, H Zheng, Y Xie
IEEE Access 10, 46796-46807, 2022
Processing system that increases the memory capacity of a gpgpu
Y Wang, D Niu, G Yijin, W Shengcheng, S Li, H Zheng
US Patent App. 17/581,728, 2023
Processing system that increases the capacity of a very fast memory
Y Wang, D Niu, G Yijin, W Shengcheng, S Li, H Zheng
US Patent App. 17/581,774, 2023
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio
Z Du, Y Guan, T Guan, D Niu, N Tan, X Yu, H Zheng, J Meng, X Yan, Y Xie
2022 IEEE 28th International Conference on Parallel and Distributed Systems …, 2023
Flexible memory extension systems and methods
D Niu, G Yijin, W Shengcheng, Y Wang, S Li, H Zheng
US Patent App. 17/866,403, 2022
Server and accelerator for neural network computations
L Liang, G Yijin, F Sun
US Patent App. 17/717,111, 2022
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs
Z Du, Y Guan, T Guan, D Niu, L Huang, H Zheng, Y Xie
IEEE Access 10, 85960-85974, 2022
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