| Memory cell comprising one MOS transistor with an isolated body having a reinforced memory effect R Ranica, A Villaret, P Mazoyer US Patent 7,541,636, 2009 | 163 | 2009 |
| A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories R Ranica, A Villaret, C Fenouillet-Beranger, P Malinge, P Mazoyer, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 132 | 2004 |
| Truly innovative 28nm FDSOI technology for automotive micro-controller applications embedding 16MB phase change memory F Arnaud, P Zuliani, JP Reynard, A Gandolfo, F Disegni, P Mattavelli, ... 2018 IEEE International Electron Devices Meeting (IEDM), 18.4. 1-18.4. 4, 2018 | 79 | 2018 |
| A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM R Ranica, A Villaret, P Malinge, P Mazoyer, D Lenoble, P Candelier, ... Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 128-129, 2004 | 48 | 2004 |
| FDSOI process/design full solutions for ultra low leakage, high speed and low voltage SRAMs R Ranica, N Planes, O Weber, O Thomas, S Haendler, D Noblet, D Croain, ... 2013 Symposium on VLSI Technology, T210-T211, 2013 | 43 | 2013 |
| A cost-effective low power platform for the 45-nm technology node E Josse, S Parihar, O Callen, P Ferreira, C Monget, A Farcy, M Zaleski, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 38 | 2006 |
| High density embedded PCM cell in 28nm FDSOI technology for automotive micro-controller applications F Arnaud, P Ferreira, F Piazza, A Gandolfo, P Zuliani, P Mattavelli, ... 2020 IEEE International Electron Devices Meeting (IEDM), 24.2. 1-24.2. 4, 2020 | 37 | 2020 |
| An 8 Mbit DRAM design using a 1 Tbulk cell P Malinge, P Candelier, F Jacquet, S Martin, R Ranica, A Villaret, ... Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005., 358-361, 2005 | 37 | 2005 |
| A new 40-nm SONOS structure based on backside trapping for nanoscale memories R Ranica, A Villaret, P Mazoyer, S Monfray, D Chanemougame, ... IEEE transactions on nanotechnology 4 (5), 581-587, 2005 | 30 | 2005 |
| Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs F Andrieu, M Cassé, E Baylac, P Perreau, O Nier, D Rideau, R Berthelon, ... 2014 44th European Solid State Device Research Conference (ESSDERC), 106-109, 2014 | 26 | 2014 |
| Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications R Ranica, A Villaret, P Malinge, G Gasiot, P Mazoyer, P Roche, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 38-39, 2005 | 18 | 2005 |
| Dynamic single-p-well SRAM bitcell characterization with back-bias adjustment for optimized wide-voltage-range SRAM operation in 28nm UTBB FD-SOI O Thomas, B Zimmer, SO Toh, L Ciampolini, N Planes, R Ranica, ... 2014 IEEE International Electron Devices Meeting, 3.4. 1-3.4. 4, 2014 | 17 | 2014 |
| 28nm FDSOI technology sub-0.6 V SRAM Vmin assessment for ultra low voltage applications R Ranica, N Planes, V Huard, O Weber, D Noblet, D Croain, F Giner, ... 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 14 | 2016 |
| Memory cell comprising one MOS transistor with an isolated body having an improved read sensitivity A Villaret, P Mazoyer, R Ranica US Patent 7,709,875, 2010 | 14 | 2010 |
| Memory cell comprising one MOS transistor with an isolated body having a prolonged memory effect R Ranica, A Villaret, P Mazoyer US Patent App. 11/479,220, 2007 | 14 | 2007 |
| Impact of tunnel etching process on electrical performances of SON devices V Caubet, S Borel, C Arvet, J Bilde, D Chanemougame, S Monfray, ... Japanese journal of applied physics 44 (7S), 5795, 2005 | 12 | 2005 |
| Crystallization speed in Ge-rich PCM cells as a function of process and programming conditions E Gomiero, G Samanni, J Jasse, C Jahan, O Weber, R Berthelon, ... IEEE Journal of the Electron Devices Society 7, 517-521, 2019 | 7 | 2019 |
| Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOS O Weber, N Planes, R Ranica US Patent 9,099,354, 2015 | 7 | 2015 |
| High-activation laser anneal process for the 45nm cmos technology platform M Bidaud, H Bono, C Chaton, B Dumont, V Huard, P Morin, ... 2007 15th International Conference on Advanced Thermal Processing of …, 2007 | 7 | 2007 |
| Improving Ge-rich GST ePCM reliability through BEOL engineering A Redaelli, A Gandolfo, G Samanni, E Gomiero, E Petroni, L Scotti, ... ESSDERC 2021-IEEE 51st European Solid-State Device Research Conference …, 2021 | 6 | 2021 |
