| Reducing memory interference in multicore systems via application-aware memory channel partitioning SP Muralidhara, L Subramanian, O Mutlu, M Kandemir, T Moscibroda Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 354 | 2011 |
| Tiered-latency DRAM: A low latency and low cost DRAM architecture D Lee, Y Kim, V Seshadri, J Liu, L Subramanian, O Mutlu High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th …, 2013 | 351 | 2013 |
| Staged memory scheduling: achieving high performance and scalability in heterogeneous systems R Ausavarungnirun, KKW Chang, L Subramanian, GH Loh, O Mutlu ACM SIGARCH Computer Architecture News 40 (3), 416-427, 2012 | 320 | 2012 |
| Research problems and opportunities in memory systems O Mutlu, L Subramanian Supercomputing frontiers and innovations 1 (3), 19, 2014 | 240 | 2014 |
| MISE: Providing performance predictability and improving fairness in shared main memory systems L Subramanian, V Seshadri, Y Kim, B Jaiyen, O Mutlu High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th …, 2013 | 222 | 2013 |
| The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory L Subramanian, V Seshadri, A Ghosh, S Khan, O Mutlu Proceedings of the 48th International Symposium on Microarchitecture, 62-75, 2015 | 220 | 2015 |
| GrandSLAm: Guaranteeing SLAs for Jobs in Microservices Execution Frameworks RS Kannan, L Subramanian, A Raju, J Ahn, J Mars, L Tang Proceedings of the Fourteenth EuroSys Conference 2019, 34, 2019 | 169 | 2019 |
| Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM D Lee, L Subramanian, R Ausavarungnirun, J Choi, O Mutlu Parallel Architecture and Compilation (PACT), 2015 International Conference …, 2015 | 150 | 2015 |
| Design-induced latency variation in modern dram chips: Characterization, analysis, and latency reduction mechanisms D Lee, S Khan, L Subramanian, S Ghose, R Ausavarungnirun, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017 | 149 | 2017 |
| Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips D Lee, S Khanℵ, L Subramanian, S Ghose, R Ausavarungnirun, ... | 149* | |
| GenASM: A high-performance, low-power approximate string matching acceleration framework for genome sequence analysis DS Cali, GS Kalsi, Z Bingöl, C Firtina, L Subramanian, JS Kim, ... 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 136 | 2020 |
| DASH: Deadline-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators H Usui, L Subramanian, KKW Chang, O Mutlu ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 65, 2016 | 132 | 2016 |
| The blacklisting memory scheduler: Achieving high performance and fairness at low cost L Subramanian, D Lee, V Seshadri, H Rastogi, O Mutlu Computer Design (ICCD), 2014 32nd IEEE International Conference on, 8-15, 2014 | 128 | 2014 |
| BLISS: Balancing performance, fairness and complexity in memory access scheduling L Subramanian, D Lee, V Seshadri, H Rastogi, O Mutlu IEEE Transactions on Parallel and Distributed Systems 27 (10), 3071-3087, 2016 | 104 | 2016 |
| A-DRM: Architecture-aware distributed resource management of virtualized clusters H Wang, C Isci, L Subramanian, J Choi, D Qian, O Mutlu ACM SIGPLAN Notices 50 (7), 93-106, 2015 | 42 | 2015 |
| The main memory system: Challenges and opportunities O Mutlu, J Meza, L Subramanian Communications of the Korean Institute of Information Scientists and Engineers, 2015 | 23 | 2015 |
| Systems and methods for page management using local page information S Srikanth, L Subramanian, S Subramoney US Patent App. 10/191,689, 2019 | 20* | 2019 |
| SQUASH: Simple QoS-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators H Usui, L Subramanian, K Chang, O Mutlu arXiv preprint arXiv:1505.07502, 2015 | 18 | 2015 |
| Scoreboard approach to managing idle page close timeout duration in memory S Srikanth, L Subramanian, S Subramoney US Patent App. 10/176,124, 2019 | 17* | 2019 |
| Reducing DRAM latency by exploiting design-induced latency variation in modern DRAM chips D Lee, S Khan, L Subramanian, R Ausavarungnirun, G Pekhimenko, ... arXiv preprint arXiv:1610.09604, 2016 | 17 | 2016 |
