Silver nanowire/colorless-polyimide composite electrode: application in flexible and transparent resistive switching memory SW Yeom, B You, K Cho, HY Jung, J Park, C Shin, BK Ju, JW Kim Scientific reports 7 (1), 3438, 2017 | 30 | 2017 |
Effect of hydrogen annealing on contact resistance reduction of metal–interlayer–n-germanium source/drain structure GS Kim, G Yoo, Y Seo, SH Kim, K Cho, BJ Cho, C Shin, JH Park, HY Yu IEEE Electron Device Letters 37 (6), 709-712, 2016 | 16 | 2016 |
Atomic Layer Deposition of TiO2 using Titanium Isopropoxide and H2O: Operational Principle of Equipment and Parameter Setting K Cho, JD Park, C Shin JSTS: Journal of Semiconductor Technology and Science 16 (3), 346-351, 2016 | 10 | 2016 |
Capacitance matching effects in negative capacitnace field effect transistor J Jo, AI Khan, K Cho, S Oh, S Salahuddin, C Shin 2016 IEEE Silicon Nanoelectronics Workshop (SNW), 174-175, 2016 | 8 | 2016 |
Utilizing Valley–Spin Hall Effect in Monolayer WSe2 for Designing Low Power Nonvolatile Spintronic Devices and Flip-Flops K Cho, X Liu, Z Chen, SK Gupta IEEE Transactions on Electron Devices 69 (4), 1667-1676, 2021 | 3 | 2021 |
WSe2 based Valley-Coupled-Spintronic Devices for Low Power Non-Volatile Memories S Thirumala, T Hung, A Raha, N Thakuria, K Cho, V Raghunathan, ... 2019 Device Research Conference (DRC), 211-212, 2019 | 3 | 2019 |
Exchange-coupling-enabled electrical-isolation of compute and programming paths in valley-spin Hall effect based spintronic device for neuromorphic applications K Cho, X Fong, SK Gupta 2021 Device Research Conference (DRC), 1-2, 2021 | 2 | 2021 |
Simulation Techniques for Nanoelectromechanical (NEM) Relay K Cho, C Shin Journal of Nanoscience and Nanotechnology 18 (9), 6615-6618, 2018 | 2 | 2018 |
XNOR-VSH: A Valley-Spin Hall Effect-based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks K Cho, A Malhotra, SK Gupta IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2023 | 1 | 2023 |
Utilizing Valley-Spin Hall Effect in WSe2 for Low Power Non-Volatile Flip-Flop Design K Cho, SK Thirumala, X Liu, N Thakuria, Z Chen, SK Gupta 2020 Device Research Conference (DRC), 1-2, 2020 | 1 | 2020 |
Amorphous Indium Zinc Oxide Thin-Film Transistor with Steep Subthreshold Slope by Negative Capacitance K Cho, J Jo, C Shin IEICE Transactions on Electronics 99 (5), 544-546, 2016 | 1 | 2016 |
2D TRANSITION METAL DICHALCOGENIDE BASED SPINTRONIC DEVICES AND CIRCUITS FOR NON-VOLATILE MEMORIES AND LOGIC K Cho Purdue University Graduate School, 2023 | | 2023 |
Valley-Spin Hall Effect-Based Nonvolatile Memory With Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths K Cho, SK Gupta IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 8 …, 2022 | | 2022 |
Experimental Observation of Negative Capacitance in Organic/Ferroelectric Capacitor for Steep Switching MOSFET Y Lee, J Jo, K Cho, S Oh, JD Park, C Shin Journal of Nanoscience and Nanotechnology 17 (5), 3469-3471, 2017 | | 2017 |
Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor H Lee, K Cho, C Shin, H Shin JSTS: Journal of Semiconductor Technology and Science 16 (2), 185-190, 2016 | | 2016 |