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Ramesh Vaddi
Ramesh Vaddi
SRM University Andhra Pradesh
Verified email at srmap.edu.in
Title
Cited by
Cited by
Year
Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS
R Vaddi, S Dasgupta, RP Agarwal
IEEE Transactions on Electron Devices 57 (3), 654-664, 2010
1362010
Tunnel FET RF rectifier design for energy harvesting applications
H Liu, X Li, R Vaddi, K Ma, S Datta, V Narayanan
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4 (4 …, 2014
992014
Device and circuit design challenges in the digital subthreshold region for ultralow-power applications
R Vaddi, S Dasgupta, RP Agarwal
VLSI Design 2009, 2009
562009
The shuttle nanoelectromechanical nonvolatile memory
V Pott, GL Chua, R Vaddi, JML Tsai, TT Kim
IEEE transactions on electron devices 59 (4), 1137-1143, 2012
522012
Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier
H Liu, R Vaddi, S Datta, V Narayanan
International Symposium on Low Power Electronics and Design (ISLPED), 157-162, 2013
422013
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options
R Vaddi, RP Agarwal, S Dasgupta
Microelectronics journal 42 (5), 798-807, 2011
372011
Compact modeling of a generic double-gate MOSFET with gate–S/D underlap for subthreshold operation
R Vaddi, RP Agarwal, S Dasgupta
IEEE Transactions on Electron Devices 59 (10), 2846-2849, 2012
342012
Design and analysis of double-gate mosfets for ultra-low power radio frequency identification (rfid): Device and circuit co-design
R Vaddi, RP Agarwal, S Dasgupta, TT Kim
Journal of Low Power Electronics and Applications 1 (2), 277-302, 2011
312011
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic
R Vaddi, S Dasgupta, RP Agarwal
Microelectronics Journal 41 (4), 195-211, 2010
312010
Low power nanoelectronics
H Liu, R Vaddi, V Narayanan, S Datta, MS Kim, X Li, A Schmid, ...
US Patent 9,800,094, 2017
232017
Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction
A Japa, H Vallabhaneni, R Vaddi
IET Circuits, Devices & Systems 10 (6), 522-527, 2016
182016
Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm
H Vallabhaneni, A Japa, S Shaik, KSR Krishna, R Vaddi
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-5, 2014
182014
Hardware security exploiting post-CMOS devices: fundamental device characteristics, state-of-the-art countermeasures, challenges and roadmap
A Japa, MK Majumder, SK Sahoo, R Vaddi, BK Kaushik
IEEE Circuits and Systems Magazine 21 (3), 4-30, 2021
152021
Negative capacitance FETs for energy efficient and hardware secure logic designs
RC Bheemana, A Japa, SS Yellampalli, R Vaddi
Microelectronics Journal 119, 105320, 2022
132022
Tunnel FET based low voltage static vs dynamic logic families for energy efficiency
K Subramanyam, S Shaik, R Vaddi
18th International Symposium on VLSI Design and Test, 1-2, 2014
132014
Chest X ray and cough sample based deep learning framework for accurate diagnosis of COVID-19
S Kumar, R Nagar, S Bhatnagar, R Vaddi, SK Gupta, M Rashid, AK Bashir, ...
Computers and Electrical Engineering 103, 108391, 2022
122022
Circuit and architectural co-design for reliable adder cells with steep slope tunnel transistors for energy efficient computing
S Shaik, KSR Krishna, R Vaddi
2016 29th International Conference on VLSI Design and 2016 15th …, 2016
122016
Design and scalability of a memory array utilizing anchor-free nanoelectromechanical nonvolatile memory device
R Vaddi, V Pott, GL Chua, JTM Lin, TT Kim
IEEE electron device letters 33 (9), 1315-1317, 2012
122012
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design
RC Bheemana, A Japa, S sankar Yellampalli, R Vaddi
Microelectronics Journal 133, 105711, 2023
102023
A low voltage capacitor based current controlled sense amplifier for input offset compensation
YS Vani, NU Rani, R Vaddi
2017 International SoC Design Conference (ISOCC), 23-24, 2017
102017
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