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Jianan Mu
Jianan Mu
Institute of Computing Technology, State Key Laboratory of Processors (SKLP), Chinese Academy of
Verified email at ict.ac.cn
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Scalable and conflict-free NTT hardware accelerator design: Methodology, proof and implementation
J Mu, Y Ren, W Wang, Y Hu, S Chen, CH Chang, J Fan, J Ye, Y Cao, H Li, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022
112022
A voltage template attack on the modular polynomial subtraction in Kyber
J Mu, Y Zhao, Z Wang, J Ye, J Fan, S Chen, H Li, X Li, Y Cao
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 672-677, 2022
52022
Energy-efficient ntt design with one-bank sram and 2-d pe array
J Mu, H Tan, J Wu, H Lu, CH Chang, S Chen, S Liang, J Ye, H Li, X Li
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-2, 2023
22023
Multi-granularity reconfiguration based physical unclonable function design
MU Jianan, J Ye, X Li, H Li, Y Hu
2020 China Semiconductor Technology International Conference (CSTIC), 1-3, 2020
12020
Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design
J Mu, H Tan, S Chen, M Cai, J Ye, H Li, X Li
2023 IEEE 32nd Asian Test Symposium (ATS), 1-6, 2023
2023
Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants
C Ma, J Mu, J Ye, S Chen, Y Cao, H Li, X Li
2023 IEEE European Test Symposium (ETS), 1-6, 2023
2023
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