| An ultra high endurance and thermally stable selector based on TeAsGeSiSe chalcogenides compatible with BEOL IC Integration for cross-point PCM HY Cheng, WC Chien, IT Kuo, EK Lai, Y Zhu, JL Jordan-Sweet, A Ray, ... 2017 IEEE International Electron Devices Meeting (IEDM), 2.2. 1-2.2. 4, 2017 | 55 | 2017 |
| Ultra-High Endurance and Low IOFF Selector based on AsSeGe Chalcogenides for Wide Memory Window 3D Stackable Crosspoint Memory HY Cheng, WC Chien, IT Kuo, CW Yeh, L Gignac, W Kim, EK Lai, YF Lin, ... 2018 IEEE International Electron Devices Meeting (IEDM), 37.3. 1-37.3. 4, 2018 | 50 | 2018 |
| A study on OTS-PCM pillar cell for 3-D stackable memory WC Chien, CW Yeh, RL Bruce, HY Cheng, IT Kuo, CH Yang, A Ray, ... IEEE Transactions on Electron Devices 65 (11), 5172-5179, 2018 | 37 | 2018 |
| Comprehensive scaling study on 3D cross-point PCM toward 1Znm node for SCM applications WC Chien, HY Ho, CW Yeh, CH Yang, HY Cheng, W Kim, IT Kuo, ... 2019 Symposium on VLSI Technology, T60-T61, 2019 | 25 | 2019 |
| High endurance self-heating OTS-PCM pillar cell for 3D stackable memory CW Yeh, WC Chien, RL Bruce, HY Cheng, IT Kuo, CH Yang, A Ray, ... 2018 IEEE Symposium on VLSI Technology, 205-206, 2018 | 18 | 2018 |
| Si incorporation into AsSeGe chalcogenides for high thermal stability, high endurance and extremely low Vth drift 3D stackable cross-point memory HY Cheng, IT Kuo, WC Chien, CW Yeh, YC Chou, N Gong, L Gignac, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 17 | 2020 |
| A no-verification multi-level-cell (MLC) operation in cross-point OTS-PCM N Gong, W Chien, Y Chou, C Yeh, N Li, H Cheng, C Cheng, I Kuo, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 16 | 2020 |
| Optimizing AsSeGe Chalcogenides by Dopants for Extremely Low IOFF, High Endurance and Low Vth Drift 3D Crosspoint Memory HY Cheng, WC Chien, IT Kuo, CH Yang, YC Chou, RL Bruce, EK Lai, ... 2021 IEEE International Electron Devices Meeting (IEDM), 28.6. 1-28.6. 4, 2021 | 12 | 2021 |
| Methods of forming semiconductor trench and forming dual trenches, and structure for isolating devices CM Ma, TW Wu, CH Yang US Patent 8,450,180, 2013 | 9 | 2013 |
| Solution for PCM and OTS intermixing on cross-point phase change memory WC Chien, LM Gignac, N Gong, CW Yeh, CH Yang, RL Bruce, HY Cheng, ... 2019 IEEE 11th International Memory Workshop (IMW), 1-4, 2019 | 7 | 2019 |
| Semiconductor device TW Wu, CM Yih, CH Yang US Patent 8,471,324, 2013 | 7 | 2013 |
| Vertical channel structure TW Wu, CH Yang US Patent 9,543,319, 2017 | 6 | 2017 |
| Superb endurance and appropriate Vth of PCM pillar cell using buffer layer for 3D cross-point memory N Gong, WC Chien, A Ray, LM Gignac, CW Yeh, CH Yang, RL Bruce, ... 2019 IEEE 11th International Memory Workshop (IMW), 1-4, 2019 | 5 | 2019 |
| Endurance evaluation on OTS-PCM device using constant current stress scheme WC Chien, LM Gignac, YC Chou, CH Yang, N Gong, HY Ho, CW Yeh, ... 2022 IEEE International Reliability Physics Symposium (IRPS), P7-1-P7-4, 2022 | 2 | 2022 |
| Device Study on OTS-PCM for Persistent Memory Application: IBM/Macronix Phase Change Memory Joint Project WC Chien, LM Gignac, YC Chou, CH Yang, N Gong, HY Ho, CW Yeh, ... 2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM …, 2022 | 1 | 2022 |
| Memory with laminated cell CH Yang, HL Lung, WC Chien, CW Cheng, MJ BrightSky US Patent App. 17/349,359, 2022 | | 2022 |
| Characterization of the low temperature activated N+/P junction formed by implant into silicide method KM Chang, JH Lin, CH Yang Applied surface science 254 (19), 6155-6157, 2008 | | 2008 |
